IEEE Transactions on Computers
Analysis and design of latch-controlled synchronous digital circuits
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Placement for clock period minimization with multiple wave propagation
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Computing optimal clock schedules
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A clustering-based optimization algorithm in zero-skew routings
DAC '93 Proceedings of the 30th international Design Automation Conference
Power optimal buffered clock tree design
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
On the bounded-skew clock and Steiner routing problems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Bounded-skew clock and Steiner routing under Elmore delay
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Useful-skew clock routing with gate sizing for low power design
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Jitter-tolerant clock routing in two-phase synchronous systems
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
An Algorithm for Zero-Skew Clock Tree Routing with Buffer Insertion
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A practical clock tree synthesis for semi-synchronous circuits
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Clustering based fast clock scheduling for light clock-tree
Proceedings of the conference on Design, automation and test in Europe
Physical aware clock skew rescheduling
Proceedings of the 17th ACM Great Lakes symposium on VLSI
System level clock tree synthesis for power optimization
Proceedings of the conference on Design, automation and test in Europe
Clock tree synthesis with pre-bond testability for 3D stacked IC designs
Proceedings of the 47th Design Automation Conference
An efficient merging scheme for prescribed skew clock routing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Clock Tree synthesis for TSV-based 3D IC designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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It is known that the clock-period can be shorter than the maximum of signal-delays between registers if the clock arrival time to each register is properly scheduled. The algorithm to design an optimal clock-schedule was given. In this paper, we propose a clock-tree routing algorithm that realizes a given clock-schedule using the Elmore-delay model. Following the deferred-merge-embedding (DME) framework, the algorithm generates a topology of the clock-tree and determines the locations and sizes of intermediate buffers simultaneously. The experimental results show that this method constructs clock-trees with moderate wire length compared with that of zero-skew clock-trees.