IEEE Transactions on Computers
Clock routing for high-performance ICs
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
High-performance clock routing based on recursive geometric matching
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Reliable non-zero skew clock trees using wire width optimization
DAC '93 Proceedings of the 30th international Design Automation Conference
A buffer distribution algorithm for high-speed clock routing
DAC '93 Proceedings of the 30th international Design Automation Conference
A clustering-based optimization algorithm in zero-skew routings
DAC '93 Proceedings of the 30th international Design Automation Conference
Low-cost single-layer clock trees with exact zero Elmore delay skew
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Skew sensitivity minimization of buffered clock tree
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A specified delay accomplishing clock router using multiple layers
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Planar-DME: improved planar zero-skew clock routing with minimum pathlength delay
EURO-DAC '94 Proceedings of the conference on European design automation
Power optimal buffered clock tree design
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
On the bounded-skew clock and Steiner routing problems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Optimization of power dissipation and skew sensitivity in clock buffer synthesis
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Bounded-skew clock and Steiner routing under Elmore delay
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A practical clock router that accounts for the capacitance derived from parallel and cross segments
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Practical Bounded-Skew Clock Routing
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
Clock-tree routing realizing a clock-schedule for semi-synchronous circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A parallel algorithm for zero skew clock tree routing
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Bounded-skew clock and Steiner routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Clock distribution using multiple voltages
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
The associative-skew clock routing problem
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Practical approximation algorithms for zero- and bounded-skew trees
SODA '01 Proceedings of the twelfth annual ACM-SIAM symposium on Discrete algorithms
Clustering based fast clock scheduling for light clock-tree
Proceedings of the conference on Design, automation and test in Europe
Low-power clock distribution using multiple voltages and reduced swings
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Saving Power by Synthesizing Gated Clocks for Sequential Circuits
IEEE Design & Test
Process variation aware clock tree routing
Proceedings of the 2003 international symposium on Physical design
Automatic clock tree generation in ASIC designs
EDTC '95 Proceedings of the 1995 European conference on Design and Test
An Algorithm for Zero-Skew Clock Tree Routing with Buffer Insertion
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Power-aware clock tree planning
Proceedings of the 2004 international symposium on Physical design
Equidistance routing in high-speed VLSI layout design
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Clock Scheduling and Clocktree Construction for High Performance ASICS
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Equidistance routing in high-speed VLSI layout design
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Process-induced skew reduction in nominal zero-skew clock trees
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Legitimate Skew Clock Routing with Buffer Insertion
Journal of VLSI Signal Processing Systems
Clock buffer and wire sizing using sequential programming
Proceedings of the 43rd annual Design Automation Conference
Low-power gated and buffered clock network construction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Clock tree synthesis with data-path sensitivity matching
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Proceedings of the 46th Annual Design Automation Conference
Equidistance routing in high-speed VLSI layout design
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Symmetrical buffer placement in clock trees for minimal skew immune to global on-chip variations
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Fast timing-model independent buffered clock-tree synthesis
Proceedings of the 47th Design Automation Conference
An efficient phase detector connection structure for the skew synchronization system
Proceedings of the 47th Design Automation Conference
Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
A dual-MST approach for clock network synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Clock tree embedding for 3D ICs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Clock network synthesis with concurrent gate insertion
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees
Proceedings of the International Conference on Computer-Aided Design
Local clock skew minimization using blockage-aware mixed tree-mesh clock network
Proceedings of the International Conference on Computer-Aided Design
On construction low power and robust clock tree via slew budgeting
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Top-down-based symmetrical buffered clock routing
Proceedings of the great lakes symposium on VLSI
Smart non-default routing for clock power reduction
Proceedings of the 50th Annual Design Automation Conference
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