On construction low power and robust clock tree via slew budgeting

Authors:
Yeh-Chi Chang;Chun-Kai Wang;Hung-Ming Chen
Affiliations:
National Chiao Tun University, Hsinchu, Taiwan Roc;National Chiao Tun University, Hsinchu, Taiwan Roc;National Chiao Tun University, Hsinchu, Taiwan Roc
Venue:
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Year:
2012

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Abstract

Clock skew resulted by process variation becomes more and more serious as technology shrinks. In 2010, ISPD held a high performance clock network synthesis contest; it considered supply-voltage variation and wire manufacturing variation. Previous works show that the main issue of variation induced skew is on supply-voltage variation. To trade off power and supply-voltage variation induced skew more effectively, we adapt a tree topology which use a timing model independent symmetrical tree at top level to drive the bottom level non-symmetry trees. Our method gives top tree more power budget to reduce supply-voltage variation induced skew and greedily saves power consuming in bottom level. Experimental results are evaluated from the benchmarks of ISPD contest 2010. Compared with state-of-the-art cross link work, the proposed technique reduces 10% of power consumption on average and also improves the run time.