FF-bond: multi-bit flip-flop bonding at placement

Authors:
Chang-Cheng Tsai;Yiyu Shi;Guojie Luo;Iris Hui-Ru Jiang
Affiliations:
National Chiao Tung University, Hsinchu, Taiwan Roc;Missouri University of Science and Technology, Rolla, MO, USA;Peking University, Beijing, China;National Chiao Tung University, Hsinchu, Taiwan Roc
Venue:
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Year:
2013

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Abstract

Clock power contributes a significant portion of chip power in modern IC design. Applying multi-bit flip-flops can effectively reduce clock power. State-of-the-art work performs multi-bit flip-flop clustering at the post-placement stage. However, the solution quality may be limited because the combinational gates are immovable during the clustering process. To overcome the deficiency, in this paper, we propose multi-bit flip-flop bonding at placement. Inspired by ionic bonding in Chemistry, we direct flip-flops to merging friendly locations thus facilitating flip-flop merging. Experimental results show that our algorithm, called FF-Bond, can save 27% clock power on average. Compared with state-of-the-art post-placement multi-bit flip-flop clustering, FF-Bond can further reduce 14% clock power.