Clock routing for high-performance ICs
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
High-performance clock routing based on recursive geometric matching
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Simultaneous buffer and wire sizing for performance and power optimization
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
A low-power design method using multiple supply voltages
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Reducing power in high-performance microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
Clock distribution using multiple voltages
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Interconnect-power dissipation in a microprocessor
Proceedings of the 2004 international workshop on System level interconnect prediction
Power-aware clock tree planning
Proceedings of the 2004 international symposium on Physical design
Temperature-aware global placement
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Automatic synthesis of low-power gated-clock finite-state machines
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power buffered clock tree design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gated clock routing for low-power microprocessor design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Net weighting to reduce repeater counts during placement
Proceedings of the 42nd annual Design Automation Conference
Supply Voltage Degradation Aware Analytical Placement
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Lens aberration aware timing-driven placement
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Floorplan driven leakage power aware IP-based SoC design space exploration
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Activity and register placement aware gated clock network design
Proceedings of the 2008 international symposium on Physical design
Low power clock buffer planning methodology in F-D placement for large scale circuit design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Zero skew clock routing in X-architecture based on an improved greedy matching algorithm
Integration, the VLSI Journal
Lens aberration aware placement for timing yield
ACM Transactions on Design Automation of Electronic Systems (TODAES)
MAkE: Multiobjective algorithm for k-way equipartitioning of a point set
Applied Soft Computing
Low Power Gated Clock Tree Driven Placement
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Stochastic power/ground supply voltage prediction and optimization via analytical placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Register placement for high-performance circuits
Proceedings of the Conference on Design, Automation and Test in Europe
An effective gated clock tree design based on activity and register aware placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power-driven flip-flop merging and relocation
Proceedings of the 2011 international symposium on Physical design
Obstacle-aware clock-tree shaping during placement
Proceedings of the 2011 international symposium on Physical design
PRICE: power reduction by placement and clock-network co-synthesis for pulsed-latch designs
Proceedings of the International Conference on Computer-Aided Design
Algorithmic tuning of clock trees and derived non-tree structures
Proceedings of the International Conference on Computer-Aided Design
Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power
Proceedings of the International Conference on Computer-Aided Design
Post-placement power optimization with multi-bit flip-flops
Proceedings of the International Conference on Computer-Aided Design
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
FF-bond: multi-bit flip-flop bonding at placement
Proceedings of the 2013 ACM international symposium on International symposium on physical design
The optimal fan-out of clock network for power minimization by adaptive gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Effective and efficient approach for power reduction by using multi-bit flip-flops
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Agglomerative-based flip-flop merging with signal wirelength optimization
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
In-placement clock-tree aware multi-bit flip-flop generation for power optimization
Proceedings of the International Conference on Computer-Aided Design
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Lowering power is one of the greatest challenges facing the IC industry today. We present a power-aware placement method that simultaneously performs (1) activity-based register clustering that reduces clock power by placing registers in the same leaf cluster of the clock trees in a smaller area and (2) activity-based net weighting that reduces net switching power by assigning a combination of activity and timing weights to the nets with higher switching rates or more critical timing. The method applies to designs with multiple clocks and gated clocks. We implemented the method and obtained experimental results on 8 real-world designs after placement, routing, extraction and analysis. The power-aware placement method achieved on average 25.3% and 11.4% reduction in net switching power and total power respectively, with 2.0% timing, 1.2% cell area and 11.5% runtime impact. This method has been incorporated into a commercial physical design tool.