Structure and interpretation of computer programs
Structure and interpretation of computer programs
Clock-tree power optimization based on RTL clock-gating
Proceedings of the 40th annual Design Automation Conference
Buffer sizing for clock power minimization subject to general skew constraints
Proceedings of the 41st annual Design Automation Conference
Navigating registers in placement for clock network minimization
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
A New Clock Mesh Buffer Sizing Methodology for Skew and Power Reduction
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
Automatic register banking for low-power clock trees
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Design of a Low Power Flip-Flop Using CMOS Deep Sub Micron Technology
ITC '10 Proceedings of the 2010 International Conference on Recent Trends in Information, Telecommunication and Computing
Post-placement power optimization with multi-bit flip-flops
Proceedings of the International Conference on Computer-Aided Design
Legalizing a placement with minimum total movement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FF-bond: multi-bit flip-flop bonding at placement
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Slack budgeting and slack to length converting for multi-bit flip-flop merging
Proceedings of the Conference on Design, Automation and Test in Europe
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Agglomerative-based flip-flop merging with signal wirelength optimization
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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We propose a power-driven flip-flop merging and relocation approach that can be applied after conventional timing-driven placement and before clock network synthesis. It targets to reduce the clock network size and thus the clock power consumption, as well as the switching power of the nets connected to the flip-flops by selectively merging flip-flops into multi-bit flip-flops and relocating them under timing and placement density constraints. The experimental results are very encouraging. For a set of benchmarks, our approach reduced the clock wirelength by 30 to 50%. Meanwhile, the switching power of signal nets connected to the flip-flops were reduced by 2 to 43%.