A Dual Dielectric Approach for Performance Aware Gate Tunneling Reduction in Combinational Circuits
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Floorplan repair using dynamic whitespace management
Proceedings of the 17th ACM Great Lakes symposium on VLSI
A morphing approach to address placement stability
Proceedings of the 2007 international symposium on Physical design
Abacus: fast legalization of standard cell circuits with minimal movement
Proceedings of the 2008 international symposium on Physical design
History-based VLSI legalization using network flow
Proceedings of the 47th Design Automation Conference
Power-driven flip-flop merging and relocation
Proceedings of the 2011 international symposium on Physical design
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
VLSI legalization with minimum perturbation by iterative augmentation
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Most tools for the placement of very large scale integrated chips work in two steps. First, the cells that have to be placed are roughly spread out over the chip area, ignoring disjointness (global placement). Then, in a second step, the cells are moved to their final position such that all overlaps are removed and all additional constraints are met (detailed placement or legalization). In this paper, we describe new ideas for legalization. We divide the task into appropriate subproblems that can be solved optimality in polynomial time. For the most important parts, even a linear running time can be shown. Together, the solutions of the subproblems can be combined to an algorithm that legalizes a placement minimizing the total (linear or squared) movement of cells. The algorithm is tested on a set of recent application specific integrated circuits and the results are compared to lower bounds showing that it computes provably good solutions (within a few percent of the optimum) even on very large industrial chips. By introducing significantly fewer violations, our legalization helps in overall design closure.