Performance-driven placement of cell based IC's
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A fast physical constraint generator for timing driven layout
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A performance driven macro-cell placement algorithm
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
An analytic net weighting approach for performance optimization in circuit placement
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A new min-cut placement algorithm for timing assurance layout design meeting net length constraint
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Analytical placement: A linear or a quadratic objective function?
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Prime: a timing-driven placement tool using a piecewise linear resistive network approach
DAC '93 Proceedings of the 30th international Design Automation Conference
RISA: accurate and efficient placement routability modeling
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Timing driven placement for large standard cell circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
NRG: global and detailed placement
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Congestion driven quadratic placement
DAC '98 Proceedings of the 35th annual Design Automation Conference
On the behavior of congestion minimization during placement
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Layout techniques supporting the use of dual supply voltages for cell-based designs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Timing influenced layout design
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A sensitivity based placer for standard cells
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Multi-center congestion estimation and minimization during placement
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Classical floorplanning harmful?
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Faster optimal single-row placement with fixed ordering
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Transformational placement and synthesis
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Modeling and minimization of routing congestion
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
A new congestion-driven placement algorithm based on cell inflation
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Timing driven placement using physical net constraints
Proceedings of the 38th annual Design Automation Conference
An effective congestion driven placement framework
Proceedings of the 2002 international symposium on Physical design
Net criticality revisited: an effective method to improve timing in physical design
Proceedings of the 2002 international symposium on Physical design
Proceedings of the 39th annual Design Automation Conference
Mongrel: hybrid techniques for standard cell placement
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2003 international workshop on System-level interconnect prediction
Timing driven force directed placement with physical net constraints
Proceedings of the 2003 international symposium on Physical design
Porosity aware buffered steiner tree construction
Proceedings of the 2003 international symposium on Physical design
A novel net weighting algorithm for timing-driven placement
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Managing power and performance for System-on-Chip designs using Voltage Islands
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Congestion minimization during placement without estimation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Force directed mongrel with physical net constraints
Proceedings of the 40th annual Design Automation Conference
Pushing ASIC performance in a power envelope
Proceedings of the 40th annual Design Automation Conference
Chip layout optimization using critical path weighting
DAC '84 Proceedings of the 21st Design Automation Conference
Analytical power/timing optimization technique for digital system
DAC '77 Proceedings of the 14th Design Automation Conference
Interconnect-power dissipation in a microprocessor
Proceedings of the 2004 international workshop on System level interconnect prediction
Probabilistic congestion prediction
Proceedings of the 2004 international symposium on Physical design
On legalization of row-based placements
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Efficient timing closure without timing driven placement and routing
Proceedings of the 41st annual Design Automation Conference
Fractional Cut: Improved Recursive Bisection Placement
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Architecting voltage islands in core-based system-on-a-chip designs
Proceedings of the 2004 international symposium on Low power electronics and design
Architecting voltage islands in core-based system-on-a-chip designs
Proceedings of the 2004 international symposium on Low power electronics and design
Temperature-aware global placement
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Combinatorial techniques for mixed-size placement
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Is probabilistic congestion estimation worthwhile?
Proceedings of the 2005 international workshop on System level interconnect prediction
Multilevel generalized force-directed method for circuit placement
Proceedings of the 2005 international symposium on Physical design
Capo: robust and scalable open-source min-cut floorplacer
Proceedings of the 2005 international symposium on Physical design
Kraftwerk: a versatile placement approach
Proceedings of the 2005 international symposium on Physical design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Navigating registers in placement for clock network minimization
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
Diffusion-based placement migration
Proceedings of the 42nd annual Design Automation Conference
Timing-driven placement by grid-warping
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
How accurately can we model timing in a placement engine?
Proceedings of the 42nd annual Design Automation Conference
A robust detailed placement for mixed-size IC designs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Multi-level placement for large-scale mixed-size IC designs
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Congestion driven incremental placement algorithm for standard cell layout
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Making fast buffer insertion even faster via approximation techniques
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Floorplan management: incremental placement for gate sizing and buffer insertion
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A faster implementation of APlace
Proceedings of the 2006 international symposium on Physical design
Computational geometry based placement migration
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
An efficient and effective detailed placement algorithm
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Robust mixed-size placement under tight white-space constraints
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A new LP based incremental timing driven placement for high performance designs
Proceedings of the 43rd annual Design Automation Conference
On whitespace and stability in physical synthesis
Integration, the VLSI Journal
FastRoute: a step to integrate global routing into placement
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Recursive Function Smoothing of Half-Perimeter Wirelength for Analytical Placement
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Fast and accurate routing demand estimation for efficient routability-driven placement
Proceedings of the conference on Design, automation and test in Europe
IPR: an integrated placement and routing algorithm
Proceedings of the 44th annual Design Automation Conference
RQL: global placement via relaxed quadratic spreading and linearization
Proceedings of the 44th annual Design Automation Conference
FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Hippocrates: First-Do-No-Harm Detailed Placement
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Timing optimization by restructuring long combinatorial paths
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Abacus: fast legalization of standard cell circuits with minimal movement
Proceedings of the 2008 international symposium on Physical design
Activity and register placement aware gated clock network design
Proceedings of the 2008 international symposium on Physical design
DPlace2.0: a stable and efficient analytical placement based on diffusion
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the 45th annual Design Automation Conference
An integrated nonlinear placement framework with congestion and porosity aware buffer planning
Proceedings of the 45th annual Design Automation Conference
Constraint-driven floorplan repair
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Lens aberration aware placement for timing yield
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Solving modern mixed-size placement instances
Integration, the VLSI Journal
Nano-CMOS Design for Manufacturability: Robust Circuit and Physical Design for Sub-65nm Technology Nodes
Guiding global placement with wire density
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Constraint graph-based macro placement for modern mixed-size circuit designs
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
FastRoute 4.0: global router with efficient via minimization
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Handbook of Algorithms for Physical Design Automation
Handbook of Algorithms for Physical Design Automation
Modern Circuit Placement: Best Practices and Results
Modern Circuit Placement: Best Practices and Results
Handling complexities in modern large-scale mixed-size placement
Proceedings of the 46th Annual Design Automation Conference
A rigorous framework for convergent net weighting schemes in timing-driven placement
Proceedings of the 2009 International Conference on Computer-Aided Design
CROP: fast and effective congestion refinement of placement
Proceedings of the 2009 International Conference on Computer-Aided Design
GRPlacer: improving routability and wire-length of global routing with circuit replacement
Proceedings of the 2009 International Conference on Computer-Aided Design
CRISP: congestion reduction by iterated spreading during placement
Proceedings of the 2009 International Conference on Computer-Aided Design
What makes a design difficult to route
Proceedings of the 19th international symposium on Physical design
Completing high-quality global routes
Proceedings of the 19th international symposium on Physical design
Logical and physical restructuring of fan-in trees
Proceedings of the 19th international symposium on Physical design
History-based VLSI legalization using network flow
Proceedings of the 47th Design Automation Conference
Register placement for high-performance circuits
Proceedings of the Conference on Design, Automation and Test in Europe
A hierarchical bin-based legalizer for standard-cell designs with minimal disturbance
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Speeding Up Physical Synthesis with Transactional Timing Analysis
IEEE Design & Test
A parallel branch-and-cut approach for detailed placement
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design for Manufacturability and Statistical Design: A Constructive Approach
Design for Manufacturability and Statistical Design: A Constructive Approach
The ISPD-2011 routability-driven placement contest and benchmark suite
Proceedings of the 2011 international symposium on Physical design
VLSI Physical Design: From Graph Partitioning to Timing Closure
VLSI Physical Design: From Graph Partitioning to Timing Closure
TSV-aware analytical placement for 3D IC designs
Proceedings of the 48th Design Automation Conference
A SimPLR method for routability-driven placement
Proceedings of the International Conference on Computer-Aided Design
Ripple: an effective routability-driven placer by iterative cell movement
Proceedings of the International Conference on Computer-Aided Design
Routability-driven analytical placement for mixed-size circuit designs
Proceedings of the International Conference on Computer-Aided Design
PRICE: power reduction by placement and clock-network co-synthesis for pulsed-latch designs
Proceedings of the International Conference on Computer-Aided Design
Post-placement power optimization with multi-bit flip-flops
Proceedings of the International Conference on Computer-Aided Design
SPIRE: a retiming-based physical-synthesis transformation system
Proceedings of the International Conference on Computer-Aided Design
SimPL: an effective placement algorithm
Proceedings of the International Conference on Computer-Aided Design
Unified analytical global placement for large-scale mixed-size circuit designs
Proceedings of the International Conference on Computer-Aided Design
Design-hierarchy aware mixed-size placement for routability optimization
Proceedings of the International Conference on Computer-Aided Design
Mixed integer programming models for detailed placement
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
The ISPD-2012 discrete cell sizing contest and benchmark suite
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Towards layout-friendly high-level synthesis
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
MAPLE: multilevel adaptive placement for mixed-size designs
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
ComPLx: A Competitive Primal-dual Lagrange Optimization for Global Placement
Proceedings of the 49th Annual Design Automation Conference
Proceedings of the 49th Annual Design Automation Conference
Structure-aware placement for datapath-intensive circuit designs
Proceedings of the 49th Annual Design Automation Conference
The DAC 2012 routability-driven placement contest and benchmark suite
Proceedings of the 49th Annual Design Automation Conference
Generation of performance constraints for layout
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On wirelength estimations for row-based placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Congestion minimization during placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal partitioners and end-case placers for standard-cell layout
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Routability-driven white space allocation for fixed-die standard-cell placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Legalizing a placement with minimum total movement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Sensitivity guided net weighting for placement-driven synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multilevel fixed-point-addition-based VLSI placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On controlling perturbation due to repeaters during quadratic placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Unified Theory of Timing Budget Management
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RBI: Simultaneous Placement and Routing Optimization Technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Seeing the Forest and the Trees: Steiner Wirelength Optimization in Placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Routability-Driven Placement and White Space Allocation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ECO-System: Embracing the Change in Placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Kraftwerk2—A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
BonnPlace: Placement of Leading-Edge Chips by Advanced Combinatorial Algorithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Nonconvex Gate Delay Modeling and Delay Optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Highly Efficient Gradient Computation for Density-Constrained Analytical Placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Metal-Density-Driven Placement for CMP Variation and Routability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Iterative placement improvement by network flow methods
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SimPL: An Effective Placement Algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
INTEGRA: Fast Multibit Flip-Flop Clustering for Clock Power Saving
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Assembling 2-D Blocks Into 3-D Chips
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Obstacle-Aware Clock-Tree Shaping During Placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Sensitivity-guided metaheuristics for accurate discrete gate sizing
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
LatchPlanner: latch placement algorithm for datapath-oriented high-performance VLSI designs
Proceedings of the International Conference on Computer-Aided Design
Place and route for massively parallel hardware-accelerated functional verification
Proceedings of the International Conference on Computer-Aided Design
ISPD 2014 benchmarks with sub-45nm technology rules for detailed-routing-driven placement
Proceedings of the 2014 on International symposium on physical design
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Given the significance of placement in IC physical design, extensive research studies performed over the last 50 years addressed numerous aspects of global and detailed placement. The objectives and the constraints dominant in placement have been revised many times over, and continue to evolve. Additionally, the increasing scale of placement instances affects the algorithms of choice for high-performance tools. We survey the history of placement research, the progress achieved up to now, and outstanding challenges.