Cost minimization of partitions into multiple devices
DAC '93 Proceedings of the 30th international Design Automation Conference
Partitioning around roadblocks: tackling constraints with intermediate relaxations
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Partitioning-based standard-cell global placement with an exact objective
Proceedings of the 1997 international symposium on Physical design
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Congestion driven quadratic placement
DAC '98 Proceedings of the 35th annual Design Automation Conference
Global routing with crosstalk constraints
DAC '98 Proceedings of the 35th annual Design Automation Conference
Modern VLSI design (2nd ed.): systems on silicon
Modern VLSI design (2nd ed.): systems on silicon
Effective partition-driven placement with simultaneous level processing and global net views
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Congestion reduction during placement based on integer programming
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Probability-based approaches to VLSI circuit partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Congestion minimization during placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient and effective placement for very large circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2003 international workshop on System-level interconnect prediction
Fast and accurate routing demand estimation for efficient routability-driven placement
Proceedings of the conference on Design, automation and test in Europe
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
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This paper addresses the problem of tackling multiple constraints simultaneously during a partitioning driven placement (PDP) process, where a larger solution space is available for constraint-satisfying optimization compared to post placement methods. A general methodology of multi-constraint satisfaction that balances violation correction and primary optimization is presented. A number of techniques are introduced to ensure its convergence and enhance its solution search capability with intermediate relaxation. Application of our approach to congestion control modeled as pin density and external net distribution balance constraints shows it effectively reduces overall congestion by 14.3% and improves chip area by 8.9%, with reasonable running time and only 1.6% increase in wire length. As far as we know, this is the first time an approach to congestion reduction during placement optimization produced good congestion improvement with very small wire length increase.