A loosely coupled parallel algorithm for standard cell placement
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Trading quality for compile time: ultra-fast placement for FPGAs
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Greedy, Prohibition, and Reactive Heuristics for Graph Partitioning
IEEE Transactions on Computers
Module placement for analog layout using the sequence-pair representation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Genetic VLSI circuit partitioning with two-dimensional geographic crossover and zigzag mapping
SAC '97 Proceedings of the 1997 ACM symposium on Applied computing
An effective general connectivity concept for clustering
Proceedings of the conference on Design, automation and test in Europe
On partitioning vs. placement rent properties
Proceedings of the 2001 international workshop on System-level interconnect prediction
Global objectives for standard cell placement
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Reporting of standard cell placement results
Proceedings of the 2001 international symposium on Physical design
Timing driven placement using physical net constraints
Proceedings of the 38th annual Design Automation Conference
FAR: fixed-points addition & relaxation based placement
Proceedings of the 2002 international symposium on Physical design
Proceedings of the 39th annual Design Automation Conference
Mongrel: hybrid techniques for standard cell placement
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Multilevel optimization for large-scale circuit placement
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Effective partition-driven placement with simultaneous level processing and global net views
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Local search for final placement in VLSI design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Congestion reduction during placement based on integer programming
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Fast Template Placement for Reconfigurable Computing Systems
IEEE Design & Test
Genetic Algorithm and Graph Partitioning
IEEE Transactions on Computers
Timing driven force directed placement with physical net constraints
Proceedings of the 2003 international symposium on Physical design
Partition-driven standard cell thermal placement
Proceedings of the 2003 international symposium on Physical design
A New Placement Method for Direct Mapping into LUT-Based FPGAs
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Congestion reduction during placement with provably good approximation bound
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A gridless multi-layer router for standard cell circuits using CTM cells
EDTC '97 Proceedings of the 1997 European conference on Design and Test
HPC-ASIA '97 Proceedings of the High-Performance Computing on the Information Superhighway, HPC-Asia '97
Macro Block Based FPGA Floorplanning
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Implementation and extensibility of an analytic placer
Proceedings of the 2004 international symposium on Physical design
An Enhanced Multilevel Algorithm for Circuit Placement
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A semi-persistent clustering technique for VLSI circuit placement
Proceedings of the 2005 international symposium on Physical design
Evaluation of placer suboptimality via zero-change netlist transformations
Proceedings of the 2005 international symposium on Physical design
The ISPD2005 placement contest and benchmark suite
Proceedings of the 2005 international symposium on Physical design
Partitioning and placement for buildable QCA circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Efficient placement and routing in grid-based networks
Proceedings of the 2005 ACM symposium on Applied computing
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Architecture and details of a high quality, large-scale analytical placer
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Partitioning and placement for buildable QCA circuits
Nano, quantum and molecular computing
RQL: global placement via relaxed quadratic spreading and linearization
Proceedings of the 44th annual Design Automation Conference
An efficient A* algorithm for the directed linear arrangement problem
WSEAS Transactions on Computers
An efficient placement and routing technique for fault-tolerant distributed embedded computing
ACM Transactions on Embedded Computing Systems (TECS)
Improving simulated annealing-based FPGA placement with directed moves
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Quantifying academic placer performance on custom designs
Proceedings of the 2011 international symposium on Physical design
Efficient and Deterministic Parallel Placement for FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Multithreaded memetic algorithm for VLSI placement problem
SEMCCO'11 Proceedings of the Second international conference on Swarm, Evolutionary, and Memetic Computing - Volume Part I
Proceedings of the International Conference on Computer-Aided Design
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We present a new approach to simulated annealing and a new hierarchical algorithm for row-based placement which has obtained the best results ever reported for a large set of MCNC benchmark circuits. Our results indicate that chip area reductions up to 15% are achieved compared with TimberWolfSC v6.0. Our new hierarchical annealing-based placement algorithm (TimberWolfSC v7.0) yields chip area reductions up to 21% while consuming up to 7.5 times less CPU time in comparison to TimberWolfSC v6.0. Furthermore, TimberWolfSC v7.0 produces lower total wire length by an average of 8% than Gordian/Domino, 11% lower wire length than Ritual/Tiger, while using comparable run time. TimberWolfSC v7.0 also supports precise timing driven placement