A performance driven macro-cell placement algorithm
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Benchmarks for layout synthesis—evolution and current status
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Analytical placement: A linear or a quadratic objective function?
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Computing edge-connectivity in multigraphs and capacitated graphs
SIAM Journal on Discrete Mathematics
A Divide-and-Conquer Algorithm for the Symmetric TridiagonalEigenproblem
SIAM Journal on Matrix Analysis and Applications
Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
NRG: global and detailed placement
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
The ISPD98 circuit benchmark suite
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Trading quality for compile time: ultra-fast placement for FPGAs
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
A multigrid tutorial: second edition
A multigrid tutorial: second edition
Edge separability based circuit clustering with application to circuit partitioning
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
PROUD: A Sea-Of-Gates Placement Algorithm
IEEE Design & Test
Iterative Methods for Sparse Linear Systems
Iterative Methods for Sparse Linear Systems
Efficient and effective placement for very large circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing closure based on physical hierarchy
Proceedings of the 2002 international symposium on Physical design
Congestion aware layout driven logic synthesis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Multilevel approach to full-chip gridless routing
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Optimality, scalability and stability study of partitioning and placement algorithms
Proceedings of the 2003 international symposium on Physical design
Benchmarking for large-scale placement and beyond
Proceedings of the 2003 international symposium on Physical design
Engineering a scalable placement heuristic for DNA probe arrays
RECOMB '03 Proceedings of the seventh annual international conference on Research in computational molecular biology
A novel framework for multilevel routing considering routability and performance
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
An enhanced multilevel routing system
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Timing-driven placement using design hierarchy guided constraint generation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Free space management for cut-based placement
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
An algebraic multigrid solver for analytical placement with layout based clustering
Proceedings of the 40th annual Design Automation Conference
Multilevel floorplanning/placement for large-scale modules using B*-trees
Proceedings of the 40th annual Design Automation Conference
Proceedings of the 2004 international symposium on Physical design
A study of netlist structure and placement efficiency
Proceedings of the 2004 international symposium on Physical design
On legalization of row-based placements
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Large-scale placement by grid-warping
Proceedings of the 41st annual Design Automation Conference
An Enhanced Multilevel Algorithm for Circuit Placement
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Fractional Cut: Improved Recursive Bisection Placement
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A Fast Crosstalk- and Performance-Driven Multilevel Routing System
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Large-Scale Circuit Placement: Gap and Promise
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Multilevel full-chip routing with testability and yield enhancement
Proceedings of the 2005 international workshop on System level interconnect prediction
Multilevel generalized force-directed method for circuit placement
Proceedings of the 2005 international symposium on Physical design
Unified quadratic programming approach for mixed mode placement
Proceedings of the 2005 international symposium on Physical design
A semi-persistent clustering technique for VLSI circuit placement
Proceedings of the 2005 international symposium on Physical design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Timing-driven placement by grid-warping
Proceedings of the 42nd annual Design Automation Conference
Routability-driven placement and white space allocation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
An integrated design flow for a via-configurable gate array
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A novel framework for multilevel full-chip gridless routing
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Optimality and scalability study of existing placement algorithms
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Multilevel full-chip gridless routing considering optical proximity correction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
An efficient and effective detailed placement algorithm
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Architecture and details of a high quality, large-scale analytical placer
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
Mixed-size placement with fixed macrocells using grid-warping
Proceedings of the 2007 international symposium on Physical design
An efficient placement and routing technique for fault-tolerant distributed embedded computing
ACM Transactions on Embedded Computing Systems (TECS)
Towards scalable placement for FPGAs
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Efficient and Deterministic Parallel Placement for FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
StarPlace: A new analytic method for FPGA placement
Integration, the VLSI Journal
Routability-driven analytical placement for mixed-size circuit designs
Proceedings of the International Conference on Computer-Aided Design
WRIP: logic restructuring techniques for wirelength-driven incremental placement
Proceedings of the great lakes symposium on VLSI
Case study for placement solutions in ispd11 and dac12 routability-driven placement contests
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Routability-driven placement for hierarchical mixed-size circuit designs
Proceedings of the 50th Annual Design Automation Conference
Analyzing System-Level Information’s Correlation to FPGA Placement
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Artificial bee colony for the standard cell placement problem
International Journal of Metaheuristics
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We have designed and implemented a new class of fast and highly scalable placement algorithms that directly handle complex constraints and achieve total wirelengths comparable to the state of the art. Our approach exploits recent advances in (i) multilevel methods for hierarchical computation, (ii) interior-point methods for nonconvex nonlinear programming, and (iii) the Fast Multipole Method for the order N evaluation of sums over the N (N - 1)/2 pairwise interactions of N components. Significant adaptation of these methods for the placement problem is required, and we have therefore developed a set of customized discrete algorithms for clustering, declustering, slot assignment, and local refinement with which the continuous algorithms are naturally combined. Preliminary test runs on benchmark circuits with up to 184,000 cells produce total wirelengths within approximately 5-10% of those of GORDIAN-L [1] in less than one tenth the run time. Such an ultra-fast placement engine is badly needed for timing convergence of the synthesis and layout phases of integrated circuit design.