Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Relaxation and clustering in a local search framework: application to linear placement
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
TimberWolf3.2: a new standard cell placement and global routing package
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Global objectives for standard cell placement
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Consistent placement of macro-blocks using floorplanning and standard-cell placement
Proceedings of the 2002 international symposium on Physical design
FAR: fixed-points addition & relaxation based placement
Proceedings of the 2002 international symposium on Physical design
Mongrel: hybrid techniques for standard cell placement
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Multilevel optimization for large-scale circuit placement
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Convergence of placement technology in physical synthesis: is placement really a point tool?
Proceedings of the 2003 international symposium on Physical design
Force directed mongrel with physical net constraints
Proceedings of the 40th annual Design Automation Conference
Implementation and extensibility of an analytic placer
Proceedings of the 2004 international symposium on Physical design
Proceedings of the 2004 international symposium on Physical design
On legalization of row-based placements
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Large-scale placement by grid-warping
Proceedings of the 41st annual Design Automation Conference
Fractional Cut: Improved Recursive Bisection Placement
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Multilevel generalized force-directed method for circuit placement
Proceedings of the 2005 international symposium on Physical design
The ISPD2005 placement contest and benchmark suite
Proceedings of the 2005 international symposium on Physical design
Optimal partitioners and end-case placers for standard-cell layout
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FastPlace 2.0: an efficient analytical placer for mixed-mode designs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Mixed-size placement with fixed macrocells using grid-warping
Proceedings of the 2007 international symposium on Physical design
IPR: an integrated placement and routing algorithm
Proceedings of the 44th annual Design Automation Conference
Placement of 3D ICs with thermal and interlayer via considerations
Proceedings of the 44th annual Design Automation Conference
Abacus: fast legalization of standard cell circuits with minimal movement
Proceedings of the 2008 international symposium on Physical design
DPlace2.0: a stable and efficient analytical placement based on diffusion
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Transition-aware decoupling-capacitor allocation in power noise reduction
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Handling complexities in modern large-scale mixed-size placement
Proceedings of the 46th Annual Design Automation Conference
RegPlace: a high quality open-source placement framework for structured ASICs
Proceedings of the 46th Annual Design Automation Conference
BIST design optimization for large-scale embedded memory cores
Proceedings of the 2009 International Conference on Computer-Aided Design
CROP: fast and effective congestion refinement of placement
Proceedings of the 2009 International Conference on Computer-Aided Design
GRPlacer: improving routability and wire-length of global routing with circuit replacement
Proceedings of the 2009 International Conference on Computer-Aided Design
Towards scalable placement for FPGAs
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
ITOP: integrating timing optimization within placement
Proceedings of the 19th international symposium on Physical design
Implementing multiphase resonant clocking on a finite-impulse response filter
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A SimPLR method for routability-driven placement
Proceedings of the International Conference on Computer-Aided Design
Ripple: an effective routability-driven placer by iterative cell movement
Proceedings of the International Conference on Computer-Aided Design
SimPL: an effective placement algorithm
Proceedings of the International Conference on Computer-Aided Design
Keep it straight: teaching placement how to better handle designs with datapaths
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Mixed integer programming models for detailed placement
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
MAPLE: multilevel adaptive placement for mixed-size designs
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
A size scaling approach for mixed-size placement
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
ComPLx: A Competitive Primal-dual Lagrange Optimization for Global Placement
Proceedings of the 49th Annual Design Automation Conference
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
SimPL: an algorithm for placing VLSI circuits
Communications of the ACM
A network-flow based algorithm for power density mitigation at post-placement stage
Proceedings of the Conference on Design, Automation and Test in Europe
Ripple 2.0: high quality routability-driven placement via global router integration
Proceedings of the 50th Annual Design Automation Conference
Rethinking the wirelength benefit of 3-D integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VLSI legalization with minimum perturbation by iterative augmentation
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Cell density-driven detailed placement with displacement constraint
Proceedings of the 2014 on International symposium on physical design
MIP-based detailed placer for mixed-size circuits
Proceedings of the 2014 on International symposium on physical design
ICCAD-2013 CAD contest in placement finishing and benchmark suite
Proceedings of the International Conference on Computer-Aided Design
POLAR: placement based on novel rough legalization and refinement
Proceedings of the International Conference on Computer-Aided Design
Hi-index | 0.04 |
In the past few years, there has been a lot of research in the area of global placement. In comparison, not much attention has been paid to the detailed placement problem. Existing detailed placers either fail to improve upon the excellent solution quality enabled by good global placers or are very slow. To handle the above problems, we focus on the detailed placement problem. We present an efficient and effective detailed placement algorithm to handle the wirelength minimization problem. The main contributions of our work are: (1) an efficient Global Swap technique to identify a pair of cells that can be swapped to reduce wirelength; (2) a flow that combines the Global Swap technique with other heuristics to produce very good wirelength; (3) an efficient single-segment clustering technique to optimally shift cells within a segment to minimize wirelength. On legalized mPL5 global placements on the IBM standard-cell benchmarks, our detailed placer can achieve 19.0%, 13.2% and 0.5% more wirelength reduction compared to Fengshui5.0, rowironing and Domino respectively. Correspondingly we are 3.6/spl times/ 2.8/spl times/ and 15/spl times/ faster. On the ISPD05 benchmarks (Gi-Joon Nam et al., 2005), we achieve 8.1% and 9.1% more wirelength reduction compared to Fengshui5.0 and rowironing respectively. Correspondingly we are 3.1/spl times/ and 2.3/spl times/ faster.