Consistent placement of macro-blocks using floorplanning and standard-cell placement
Proceedings of the 2002 international symposium on Physical design
Min-max placement for large-scale timing optimization
Proceedings of the 2002 international symposium on Physical design
The scaling challenge: can correct-by-construction design help?
Proceedings of the 2003 international symposium on Physical design
Benchmarking for large-scale placement and beyond
Proceedings of the 2003 international symposium on Physical design
Fine-Grain Conjunction Scheduling for Symbolic Reachability Analysis
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
FORCE: a fast and easy-to-implement variable-ordering heuristic
Proceedings of the 13th ACM Great Lakes symposium on VLSI
A study of netlist structure and placement efficiency
Proceedings of the 2004 international symposium on Physical design
On legalization of row-based placements
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Practical slicing and non-slicing block-packing without simulated annealing
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Placement feedback: a concept and method for better min-cut placements
Proceedings of the 41st annual Design Automation Conference
Fractional Cut: Improved Recursive Bisection Placement
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Large-Scale Circuit Placement: Gap and Promise
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Combinatorial techniques for mixed-size placement
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Are floorplan representations important in digital design?
Proceedings of the 2005 international symposium on Physical design
Capo: robust and scalable open-source min-cut floorplacer
Proceedings of the 2005 international symposium on Physical design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Routability-driven placement and white space allocation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Unification of partitioning, placement and floorplanning
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Multilevel expansion-based VLSI placement with blockages
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
SAT-based optimal hypergraph partitioning with replication
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Floorplan management: incremental placement for gate sizing and buffer insertion
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Seeing the forest and the trees: Steiner wirelength optimization in placemen
Proceedings of the 2006 international symposium on Physical design
Effective linear programming based placement methods
Proceedings of the 2006 international symposium on Physical design
Satisfying whitespace requirements in top-down placement
Proceedings of the 2006 international symposium on Physical design
An efficient and effective detailed placement algorithm
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Fast wire length estimation by net bundling for block placement
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Abacus: fast legalization of standard cell circuits with minimal movement
Proceedings of the 2008 international symposium on Physical design
An effective approach for large scale floorplanning
Proceedings of the 20th symposium on Great lakes symposium on VLSI
New placement prediction and mitigation techniques for local routing congestion
Proceedings of the International Conference on Computer-Aided Design
Mixed integer programming models for detailed placement
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Hierarchical congregated ant system for bottom-up VLSI placements
Engineering Applications of Artificial Intelligence
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
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We study alternatives to classic Fiduccia-Mattheyses (FM)-based partitioning algorithms in the context of end-case processing for top-down standard-cell placement. While the divide step in the top-down divide and conquer is usually performed heuristically, we observe that optimal solutions can be found for many sufficiently small partitioning instances. Our main motivation is that small partitioning instances frequently contain multiple cells that are larger than the prescribed partitioning tolerance, and that cannot be moved iteratively while preserving the legality of a solution. To sample the suboptimality of FM-based partitioning algorithms, we focus on optimal partitioning and placement algorithms based on either enumeration or branch-and-bound that are invoked for instances below prescribed size thresholds, e.g., <10 cells for placement and <30 cells for partitioning. Such partitioners transparently handle tight balance constraints and uneven cell sizes while typically achieving 40% smaller cuts than best of several FM starts for instances between ten and 50 movable nodes and average degree 2-3. Our branch-and-bound codes incorporate various efficiency improvements, using results for hypergraphs (1993) and a graph-specific algorithm (1996). We achieve considerable speed-ups over single FM starts on such instances on average. Enumeration-based partitioners relying on Gray codes, while easier to implement and taking less time for elementary operations, can only compete with branch-and-bound on very small instances, where optimal placers achieve reasonable performance as well. In the context of a top-down global placer, the right combination of optimal partitioners and placers can achieve up to an average of 10% wirelength reduction and 50% CPU time savings for a set of industry testcases. Our results show that run-time versus quality tradeoffs may be different for small problem instances than for common large benchmarks, resulting in different comparisons of optimization algorithms. We therefore suggest that alternative algorithms be considered and, as an example, present detailed comparisons with the flow-based balanced partitioner heuristic