Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Faster optimal single-row placement with fixed ordering
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Improved algorithms for hypergraph bipartitioning
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Design and implementation of move-based heuristics for VLSI hypergraph partitioning
Journal of Experimental Algorithmics (JEA)
Routability driven white space allocation for fixed-die standard-cell placement
Proceedings of the 2002 international symposium on Physical design
Toward CAD-IP Reuse: A Web Bookshelf of Fundamental Algorithms
IEEE Design & Test
Free space management for cut-based placement
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Constructive benchmarking for placement
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Placement feedback: a concept and method for better min-cut placements
Proceedings of the 41st annual Design Automation Conference
Fractional Cut: Improved Recursive Bisection Placement
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Combinatorial techniques for mixed-size placement
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Unification of partitioning, placement and floorplanning
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Optimal redistribution of white space for wire length minimization
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Optimal partitioners and end-case placers for standard-cell layout
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hierarchical whitespace allocation in top-down placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Benchmarking for large-scale placement and beyond
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimality study of logic synthesis for LUT-based FPGAs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
A tale of two nets: studies of wirelength progression in physical design
Proceedings of the 2006 international workshop on System-level interconnect prediction
Solving hard instances of floorplacement
Proceedings of the 2006 international symposium on Physical design
Effective linear programming based placement methods
Proceedings of the 2006 international symposium on Physical design
Net cluster: a net-reduction based clustering preprocessing algorithm
Proceedings of the 2006 international symposium on Physical design
Architecture and details of a high quality, large-scale analytical placer
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Mixed-size placement via line search
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Constraint-driven floorplan repair
Proceedings of the 43rd annual Design Automation Conference
Mixed-size placement with fixed macrocells using grid-warping
Proceedings of the 2007 international symposium on Physical design
An effective clustering algorithm for mixed-size placement
Proceedings of the 2007 international symposium on Physical design
Fast and robust quadratic placement combined with an exact linear net model
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement
Integration, the VLSI Journal
Abacus: fast legalization of standard cell circuits with minimal movement
Proceedings of the 2008 international symposium on Physical design
On modeling and testing of lithography related open faults in nano-CMOS circuits
Proceedings of the conference on Design, automation and test in Europe
Solving modern mixed-size placement instances
Integration, the VLSI Journal
Placement based multiplier rewiring for cell-based designs
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Improved performance and yield with chip master planning design methodology
Proceedings of the 19th ACM Great Lakes symposium on VLSI
RegPlace: a high quality open-source placement framework for structured ASICs
Proceedings of the 46th Annual Design Automation Conference
Configuration Merging in Point-to-Point Networks for Module-Based FPGA Reconfiguration
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A study of routability estimation and clustering in placement
Proceedings of the 2009 International Conference on Computer-Aided Design
The impact of interconnect architecture on via-programmed structured ASICs (VPSAs)
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
PASAP: power aware structured ASIC placement
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Integration, the VLSI Journal
Placement for immunity of transient faults in cell-based design of nanometer circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Through-silicon-via management during 3D physical design: when to add and how many?
Proceedings of the International Conference on Computer-Aided Design
SimPL: an effective placement algorithm
Proceedings of the International Conference on Computer-Aided Design
Keep it straight: teaching placement how to better handle designs with datapaths
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Proceedings of the 49th Annual Design Automation Conference
A Scheduling Strategy for Synchronous Elastic Designs
Fundamenta Informaticae - Application of Concurrency to System Design, the Eighth Special Issue
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
SimPL: an algorithm for placing VLSI circuits
Communications of the ACM
Cell transformations and physical design techniques for 3D monolithic integrated circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Artificial bee colony for the standard cell placement problem
International Journal of Metaheuristics
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In this invited note we describe Capo, an open-source software tool for cell placement, mixed-size placement and floorplanning with emphasis on routability. Capo is among the fastest academic placers and scales to millions of movable objects. This note surveys the overall structure of Capo, discusses recent improvements and describes ongoing research.