Capo: robust and scalable open-source min-cut floorplacer
Proceedings of the 2005 international symposium on Physical design
mPL6: enhanced multilevel mixed-size placement
Proceedings of the 2006 international symposium on Physical design
FPGA dynamic power minimization through placement and routing constraints
EURASIP Journal on Embedded Systems
Placement challenges for structured ASICs
Proceedings of the 2008 international symposium on Physical design
Clock power reduction for virtex-5 FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
RegPlace: a high quality open-source placement framework for structured ASICs
Proceedings of the 46th Annual Design Automation Conference
An integer programming placement approach to FPGA clock power reduction
Proceedings of the 16th Asia and South Pacific Design Automation Conference
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Structured ASICs provide an exciting middle ground between FPGA and ASIC design methodologies. Compared to ASIC, structured ASIC based designs require lower non recurring engineering (NRE) costs and turn-around-time but suffer from higher power consumption and lower performance. Power reduction for structured ASICs uses extensive clock and supply power-down of unused circuitry and use of low power devices. However, due to the limited granularity of power-down, physical design (specially placement) should be performed to maximize the components that can be powered down. In this paper, we present the first placement algorithm to specifically target this problem. Our tool, PASAP (Power Aware Structured ASIC Placement), minimizes the clock and leakage power by maximizing the fraction of the structured ASIC that can be powered down or disconnected from clock tree. On a set of large benchmark designs, PASAP reduces clock and leakage power by 32% and 17% respectively compared to prior structured ASIC placement tool RegPlace incurring 17% penalty in wirelength and 30% longer runtime.