Integrated floorplanning and interconnect planning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Buffer block planning for interconnect planning and prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Interconnect Planning with Local Area Constrained Retiming
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Revisiting VLSI Interconnects in Deep Sub-Micron: Some Open Questions
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Wire Planning with Bounded Over-the-Block Wires
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Capo: robust and scalable open-source min-cut floorplacer
Proceedings of the 2005 international symposium on Physical design
Dragon2005: large-scale mixed-size placement tool
Proceedings of the 2005 international symposium on Physical design
Fast timing closure by interconnect criticality driven delay relaxation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
High-Performance Embedded Computing: Architectures, Applications, and Methodologies
High-Performance Embedded Computing: Architectures, Applications, and Methodologies
Performance and yield enhancement of FPGAs with within-die variation using multiple configurations
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Improved timing closure by early buffer planning in floor-placement design flow
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Evaluation, prediction and reduction of routing congestion
Microelectronics Journal
An integrated nonlinear placement framework with congestion and porosity aware buffer planning
Proceedings of the 45th annual Design Automation Conference
Practical Problems in VLSI Physical Design Automation
Practical Problems in VLSI Physical Design Automation
DUNE-a multilayer gridless routing system
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A practical methodology for early buffer and wire resource allocation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simultaneous floor plan and buffer-block optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Buffer planning as an Integral part of floorplanning with consideration of routing congestion
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Interconnect mis-prediction is a major problem in nano-scale design that may diminish the quality of physical design algorithms or may even result in design divergence. In this paper, a new interconnect-planning methodology based on assume and enforce strategy is presented. In this methodology, some regions of the chip are planned to provide auxiliary routing resources and improve the interconnect delay of critical nets during the floor-placement process. Each of these wealthy regions is called a highway-on-chip. The location of highways and their resources are gradually determined during the hierarchical floor-placement process. Experimental results show that the performance, timing yield, predictability and power consumption of the attempted benchmarks are improved by 13.66%, 10.02%, 20.11%, and 6.83% on average. These improvements are obtained at the cost of about 7.82% runtime overhead and less than 0.8% wirelength growth.