Wire Planning with Bounded Over-the-Block Wires

Authors:
Hua Xiang;I-Min Liu;Martin D. F. Wong
Affiliations:
IBM T.J. Watson Research Center, Yorktown Heights, NY;Cadence Design System, San Jose, CA;UIUC, Urbana, IL
Venue:
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Year:
2005

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Abstract

Hierarchical approach greatly facilitates large-scale chip design by hiding distracting details in low-level objects. However, the low-level designs have to have a global view of high-level object connections so that some resources can be allocated in advance, and this makes wire planning an important issue in physical design. In this paper, we present two exact polynomial-time algorithms for wire planning with bounded over-the-block wires. The constraints on over-the-block wires help the longest over-the-block wires within a block to satisfy signal integrity without buffer inserted. Both algorithms guarantee to find an optimal routing solution for a two-pin net as long as one exists. One requires less memory,while the other may take less running time when processing a large number of nets. According to different application requirements, users can choose an appropriate one.