Wire Planning with Bounded Over-the-Block Wires
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Improving run times by pruned application of synthesis transforms
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
POMR: a power-aware interconnect optimization methodology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.03 |
The authors address the problem of simultaneous routing and buffer insertion. Recently the authors considered simultaneous maze routing and buffer insertion under the Elmore delay model. Their algorithms can take into account both routing obstacles and restrictions on buffer locations. It is well known that the Elmore delay is only a first-order approximation of signal delay and hence could be very inaccurate. Moreover, constraints cannot be imposed on the transition times of the output signal waveform at the sink or at the buffers on the route. The authors extend the algorithm in so that accurate delay models (e.g., transmission line model, delay lookup table from SPICE, etc.) can be used. They show that the problem of finding a minimum-delay buffered routing path can be formulated as a shortest path problem in a specially constructed weighted graph. By including only the vertices with qualifying transition times in the graph, they guarantee that all transition time constraints are satisfied. Their algorithm can be easily extended to handle buffer sizing and wire sizing. It can be applied iteratively to improve any given routing tree solution. Experimental results show that their algorithm performs well.