Gate sizing for constrained delay/power/area optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Buffer insertion with accurate gate and interconnect delay computation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Transformational placement and synthesis
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Physical synthesis methodology for high performance microprocessors
Proceedings of the 40th annual Design Automation Conference
Analytical power/timing optimization technique for digital system
DAC '77 Proceedings of the 14th Design Automation Conference
Timing
Maze routing with buffer insertion under transition time constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we describe methods to speed up integrated placement and synthesis of high performance designs. We present an analysis of the computation times of various logic synthesis transforms. We then show techniques to reduce computation time based upon judicious selection of gates and nets for the resizing and buffering transforms, respectively. We show that it is possible to obtain savings of up to 28% in CPU time without compromising the quality of the results. For large high performance designs that are quite common these days our savings could translate into several hours of CPU time.