Introduction to Switching Theory and Logical Design
Introduction to Switching Theory and Logical Design
An experimental system for power/timing optimization of LSI chips
DAC '77 Proceedings of the 14th Design Automation Conference
Aesop: a tool for automated transistor sizing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Timing verification and the timing analysis program
25 years of DAC Papers on Twenty-five years of electronic design automation
Algorithms for library-specific sizing of combinational logic
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
New algorithms for gate sizing: a comparative study
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Integrated resynthesis for low power
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Electrical optimization of PLAs
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Post-layout optimization of power and timing for ECL LSIs
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Gate Sizing: A General Purpose Optimization Approach
EDTC '96 Proceedings of the 1996 European conference on Design and Test
An experimental system for power/timing optimization of LSI chips
DAC '77 Proceedings of the 14th Design Automation Conference
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
Improving run times by pruned application of synthesis transforms
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
An analytical approach to placement legalization
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Timing analysis of computer hardware
IBM Journal of Research and Development
Transistor sizing for large combinational digital CMOS circuits
Integration, the VLSI Journal
ComPLx: A Competitive Primal-dual Lagrange Optimization for Global Placement
Proceedings of the 49th Annual Design Automation Conference
Progress and challenges in VLSI placement research
Proceedings of the International Conference on Computer-Aided Design
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A method for logic gate delay assignment is described which achieves power minimization of digital logic while satisfying system timing. The logic gates are described by a single design parameter macromodel. A Newton optimization scheme is employed using exact sparse updating. Systems consisting of up to 1200 digital logic gates have been optimized. A companion paper describes how a further optimization of the system is achieved if power-oriented placement improvement is included in the optimization procedure.