A critical path delay check system
DAC '81 Proceedings of the 18th Design Automation Conference
Design verification and performance analysis
DAC '78 Proceedings of the 15th Design Automation Conference
Computer-aided prediction of delays in LSI logic systems
DAC '73 Proceedings of the 10th Design Automation Workshop
Verification of timing constraints on large digital systems
DAC '80 Proceedings of the 17th Design Automation Conference
Analytical power/timing optimization technique for digital system
DAC '77 Proceedings of the 14th Design Automation Conference
An experimental system for power/timing optimization of LSI chips
DAC '77 Proceedings of the 14th Design Automation Conference
Practical experiences from signal probability simulation of digital designs
DAC '77 Proceedings of the 14th Design Automation Conference
Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Selection of Potentially Testable Path Delay Faults for Test Generation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Delay optimization of linear depth boolean circuits with prescribed input arrival times
Journal of Discrete Algorithms
Timing modeling of latch-controlled sub-systems
Integration, the VLSI Journal
The delay of circuits whose inputs have specified arrival times
Discrete Applied Mathematics
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Partitioning and floor-planning for data-path chip (microprocessor) layout
Integration, the VLSI Journal
Gate sizing for large cell-based designs
Proceedings of the Conference on Design, Automation and Test in Europe
Statistical delay fault coverage and defect level for delay faults
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Delay test generation 1: concepts and coverage metrics
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Proceedings of the 49th Annual Design Automation Conference
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Timing Analysis is a design automation program that assists computer design engineers in locating problem timing in a clocked, sequential machine. The program is effective for large machines because, in part, the running time is proportional to the number of circuits. This is in contrast to alternative techniques such as delay simulation, which requires large numbers of test patterns, and path tracing, which requires tracing of all paths. The output of Timing Analysis includes "Slack" at each block to provide a measure of the severity of any timing problem. The program also generates standard deviations for the times so that a statistical timing design can be produced rather than a worst case approach. This system has successfully detected all but a few timing problems for the IBM 3081 Processor Unit (consisting of almost 800 000 circuits) prior to the hardware debugging of timing. The 3081 is characterized by a tight statistical timing design.