A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '77 Proceedings of the 14th Design Automation Conference
IEEE Design & Test
SMART And FAST: Test Generation for VLSI Scan-Design Circuits
IEEE Design & Test
Timing analysis of computer hardware
IBM Journal of Research and Development
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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Physical defects in integrated circuits can sometimes degrade the circuit performance without altering the logical function. The increase in circuit delay can be small enough to cause only some of the longer paths through the fault site to fail. Also, a test for a fault of a certain size may not detect a larger fault of the same type (slow-to-rise or slow-to-fall) at the same site. This paper presents a novel approach to test for such delay faults. A variable size delay fault model is used to represent these failures. The nominal gate delays with the manufacturing tolerances are an integral part of the model and are used in the propagation of simplified waveforms through the logic network. The faulty waveforms are functions of the variable size delay fault. For each fault and test pattern, we compute a threshold ɛ such that this fault is detected if its size exceeds ɛ. This threshold is used (along with the minimum slack at the the fault site) to determine a new metric called "quality". The quality of detection for a fault measures how close the test came to exposing the ideally smallest size fault at that point. This new metric (together with the traditional fault coverage) gives a complete measure of the "goodness" of the test. A companion paper uses these concepts and develops the algebra and algorithms to generate tests for these delay faults.