Introduction to an LSI test system
DAC '77 Proceedings of the 14th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Automatic checking of logic design structures For compliance with testability ground rules
DAC '77 Proceedings of the 14th Design Automation Conference
Test generation for large logic networks
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '77 Proceedings of the 14th Design Automation Conference
A logic design structure for LSI testability
25 years of DAC Papers on Twenty-five years of electronic design automation
A logic chip delay-test method based on system timing
IBM Journal of Research and Development
Delay fault models and test generation for random logic sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Delay test effectiveness evaluation of LSSD-based VLSI logic circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A Test Methodology for High Performance MCMs
Journal of Electronic Testing: Theory and Applications - Special issue on multi-chip testing and design for testability
A delay test system for high speed logic LSI's
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Introduction to an LSI test system
DAC '77 Proceedings of the 14th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Automatic checking of logic design structures For compliance with testability ground rules
DAC '77 Proceedings of the 14th Design Automation Conference
Test generation for large logic networks
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '77 Proceedings of the 14th Design Automation Conference
Test Generation for Path-Delay Faults in One-dimensional Iterative Logic Arrays
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Design for Testability A Survey
IEEE Transactions on Computers
An Experimental Delay Test Generator for LSI Logic
IEEE Transactions on Computers
Delay test generation 1: concepts and coverage metrics
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
LSI logic testing: an overview
IEEE Transactions on Computers
Automatic test pattern generation
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
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The delay test simulator described here has two functions. First, it computes the actual timing to be used for each delay test. This computation requires delay distributions and tester tolerances. Second, it performs a parallel fault simulation to determine which delay faults have been detected.