A logic chip delay-test method based on system timing
IBM Journal of Research and Development
Analysis of timing failures due to random AC defects in VLSI modules
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '77 Proceedings of the 14th Design Automation Conference
DAC '77 Proceedings of the 14th Design Automation Conference
Evaluation of the statistical delay quality model
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
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