Quality level and fault coverage for multichip modules
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '77 Proceedings of the 14th Design Automation Conference
A logic chip delay-test method based on system timing
IBM Journal of Research and Development
Delay test effectiveness evaluation of LSSD-based VLSI logic circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
The Total Delay Fault Model and Statistical Delay Fault Coverage
IEEE Transactions on Computers
A novel approach to delay-fault diagnosis
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Enhancing test efficiency for delay fault testing using multiple-clocked schemes
Proceedings of the 39th annual Design Automation Conference
A Statistical Model for Delay-Fault Testing
IEEE Design & Test
Delay-Fault Diagnosis by Critical-Path Tracing
IEEE Design & Test
On theoretical and practical considerations of path selection for delay fault testing
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
DFSIM: A Gate-Delay Fault Simulator for Sequential Circuits
EDTC '96 Proceedings of the 1996 European conference on Design and Test
An optimized BIST test pattern generator for delay testing
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
On the fault coverage of delay fault detecting tests
EURO-DAC '90 Proceedings of the conference on European design automation
Statistical delay fault coverage and defect level for delay faults
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
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This paper presents an analytical model for projecting the yield loss due to random delay defects for modules or VLSI packages containing multiple semiconductor chips. A module to be analyzed is characterized by distribution of path delays. Statistical analysis is applied to obtain the distribution of delays caused by defects in logic circuits of LSI chips. The model uses these two distributions to calculate the probability that a module contains a path that does not meet the system timing requirements. All inputs to the model can be obtained much earlier than the availability of modules for actual testing. Therefore expected module yield loss due to delay defects can be projected before the modules are actually manufactured.