Accelerated transition fault simulation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Analysis of timing failures due to random AC defects in VLSI modules
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
DAC '77 Proceedings of the 14th Design Automation Conference
Delay fault models and test generation for random logic sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A novel approach to delay-fault diagnosis
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
On testing wave pipelined circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Test Generation for Path Delay Faults Using Binary Decision Diagrams
IEEE Transactions on Computers
A new delay test based on delay defect detection within slack intervals (DDSI)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Existing methodologies for determining gate delay fault coverages are shown to have certain deficiencies. A new and more realistic delay model is presented with the ultimate goal of ensuring error-free circuit operation through obtaining true fault coverages that extend upto the actual slacks. Methods are given that achieve such coverages when possible. Results of experiments performed to evaluate the practical benefits of the proposed methods over previous approaches are given. The proposed method over previous approaches are given. The proposed method based on varying the sampling time of the circuit outputs during testing is seen to produce very high delay fault coverages upto the actual circuit slacks, as opposed to methods based on fixed output sampling times.