Neighbor selection for variance reduction in I_DDQ and other parametric data
Proceedings of the IEEE International Test Conference 2001
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Scan Latch Design for Delay Test
Proceedings of the IEEE International Test Conference
Delay Testing with Clock Control: An Alternative to Enhanced Scan
Proceedings of the IEEE International Test Conference
Delay Test: The Next Frontier for LSSD Test Systems
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Synthesizing for Scan Dependence in Built-In Self-Testable Designs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
On Path-Delay Testing in a Standard Scan Environment
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Can DFT Totally Delete Traditional Functional Testing?'
ITC '00 Proceedings of the 2000 IEEE International Test Conference
On the fault coverage of delay fault detecting tests
EURO-DAC '90 Proceedings of the conference on European design automation
Reduce Yield Loss in Delay Defect Detection in Slack Interval
ATS '04 Proceedings of the 13th Asian Test Symposium
On Hazard-free Patterns for Fine-delay Fault Testing
ITC '04 Proceedings of the International Test Conference on International Test Conference
On the fault coverage of gate delay fault detecting tests
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Testing resistive opens and bridging faults through pulse propagation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a new technique for detecting delay faults by observing the fault effects within slack intervals. Delay faults are detected through a comparison of the circuit outputs captured in the scan flip-flops with those from a matched known good neighboring die on the wafer. These outputs are captured in the flip-flops at multiple capture intervals, each progressively shorter than the nominal switching delay for the logic block. Specially designed test chips were designed and tested to verify the applicability of the methodology. Simulation studies were also conducted to investigate the effectiveness of the technique. The results presented here clearly establish the significant potential of the proposed new delay testing approach.