A Scan-BIST Structure to Test Delay Faults in Sequential Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Distributed BIST Architecture to Combat Delay Faults
Journal of Electronic Testing: Theory and Applications
Fast test application technique without fast scan clocks
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing
Journal of Electronic Testing: Theory and Applications
Design for Delay Testability in High-Speed Digital ICs
Journal of Electronic Testing: Theory and Applications
Bridging the Testing Speed Gap: Design for Delay Testability
ETW '00 Proceedings of the IEEE European Test Workshop
Analyzing the Need for ATPG Targeting GOS Defects
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Path-Delay Fault Diagnosis in Non-Scan Sequential Circuits with At-Speed Test Application
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Testability Evaluation of Sequential Designs Incorporating the Multi-Mode Scannable Memory Element
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Scan Latch Design for Test Applications
Journal of Electronic Testing: Theory and Applications
A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Low Voltage Test in Place of Fast Clock in DDSI Delay Test
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique
Journal of Electronic Testing: Theory and Applications
A new delay test based on delay defect detection within slack intervals (DDSI)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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