IEEE Design & Test
High-Performance Circuit Testing with Slow-Speed Testers
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Scan Latch Design for Delay Test
Proceedings of the IEEE International Test Conference
Intrinsic Leakage in Low-Power Deep Submicron CMOS ICs
Proceedings of the IEEE International Test Conference
So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment
Proceedings of the IEEE International Test Conference
Digital oscillation-test method for delay and stuck-at fault testing of digital circuits
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A BIST scheme for the detection of path-delay faults
ITC '98 Proceedings of the 1998 IEEE International Test Conference
On the Generation of Pseudo-Deterministic Two-Patterns Test Sequence with LFSRs
EDTC '97 Proceedings of the 1997 European conference on Design and Test
An optimized BIST test pattern generator for delay testing
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
A Low-Speed BIST Framework for High-Performance Circuit Testing
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
A DFT Technique for High Performance Circuit Testing
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers
Journal of Electronic Testing: Theory and Applications
Evolution of test programs exploiting a FSM processor model
EvoApplications'11 Proceedings of the 2011 international conference on Applications of evolutionary computation - Volume Part II
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The economic testing of high-speed digital ICs is becoming increasingly problematic. Even advanced, expensive testers are not always capable of testing these ICs because of their high-speed limitations. This paper focuses on a Design for Delay Testability technique such that high-speed ICs can be tested using inexpensive, low-speed ATE. In addition, extensions for possible full BIST of delay faults are addressed.