ATPG for heat dissipation minimization during scan testing
DAC '97 Proceedings of the 34th annual Design Automation Conference
On the test of microprocessor IP cores
Proceedings of the conference on Design, automation and test in Europe
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Bridging the Testing Speed Gap: Design for Delay Testability
ETW '00 Proceedings of the IEEE European Test Workshop
FRITS " A Microprocessor Functional BIST Method
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Automatic Test Program Generation: A Case Study
IEEE Design & Test
New Challenges in Delay Testing of Nanometer, Multigigahertz Designs
IEEE Design & Test
DFT of the Cell Processor and its Impact on EDA Test Softwar
ATS '06 Proceedings of the 15th Asian Test Symposium
Practical Design Verification
Microprocessor Software-Based Self-Testing
IEEE Design & Test
Systematic software-based self-test for pipelined processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Microprocessor testing is becoming a challenging task, due to the increasing complexity of modern architectures. Nowadays, most architectures are tackled with a combination of scan chains and Software-Based Self-Test (SBST) methodologies. Among SBST techniques, evolutionary feedback-based ones prove effective in microprocessor testing: their main disadvantage, however, is the considerable time required to generate suitable test programs. A novel evolutionary-based approach, able to appreciably reduce the generation time, is presented. The proposed method exploits a high-level representation of the architecture under test and a dynamically built Finite State Machine (FSM) model to assess fault coverage without resorting to time-expensive simulations on low-level models. Experimental results, performed on an OpenRISC processor, show that the resulting test obtains a nearly complete fault coverage against the targeted fault model.