A scalable software-based self-test methodology for programmable processors
Proceedings of the 40th annual Design Automation Conference
Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Software-Based Self-Testing of Embedded Processors
IEEE Transactions on Computers
New evolutionary techniques for test-program generation for complex microprocessor cores
GECCO '05 Proceedings of the 7th annual conference on Genetic and evolutionary computation
Automatic generation of test sets for SBST of microprocessor IP cores
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Software-based self-test methodology for crosstalk faults in processors
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Optimal periodic testing of intermittent faults in embedded pipelined processor applications
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A Self Test Program Design Technique for Embedded DSP Cores
Journal of Electronic Testing: Theory and Applications
Systematic software-based self-test for pipelined processors
Proceedings of the 43rd annual Design Automation Conference
Simulation-Based Functional Test Generation for Embedded Processors
IEEE Transactions on Computers
Software-based self-testing with multiple-level abstractions for soft processor cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A hybrid software-based self-testing methodology for embedded processor
Proceedings of the 2008 ACM symposium on Applied computing
On efficient generation of instruction sequences to test for delay defects in a processor
Proceedings of the 18th ACM Great Lakes symposium on VLSI
CASP: concurrent autonomous chip self-test using stored test patterns
Proceedings of the conference on Design, automation and test in Europe
Functional self-testing for bus-based symmetric multiprocessors
Proceedings of the conference on Design, automation and test in Europe
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Operating system scheduling for efficient online self-test in robust systems
Proceedings of the 2009 International Conference on Computer-Aided Design
Post-silicon validation opportunities, challenges and recent advances
Proceedings of the 47th Design Automation Conference
Using introspective software-based testing for post-silicon debug and repair
Proceedings of the 47th Design Automation Conference
Structural and functional test of IBM system z10 chips
IBM Journal of Research and Development
Reducing the storage requirements of a test sequence by using a background vector
Proceedings of the Conference on Design, Automation and Test in Europe
A self-adaptive system architecture to address transistor aging
Proceedings of the Conference on Design, Automation and Test in Europe
On-Chip Delay Measurement Based Response Analysis for Timing Characterization
Journal of Electronic Testing: Theory and Applications
Fast enhancement of validation test sets for improving the stuck-at fault coverage of RTL circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Built-in functional tests for silicon validation and system integration of telecom SoC designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Systematic software-based self-test for pipelined processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Evolution of test programs exploiting a FSM processor model
EvoApplications'11 Proceedings of the 2011 international conference on Applications of evolutionary computation - Volume Part II
Software-Based Testing for System Peripherals
Journal of Electronic Testing: Theory and Applications
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This paper describes a novel functional Built-in-Self-Test method for microprocessors. This technique is based on the fundamental principle that complex chips have embedded functionality that can be used to implement a comprehensive self-test strategy. Functional testing has generally been associated with expensive testers. In order to lower the cost of test, there is a general trend to adopt structural test techniques like scan that enable use of low cost testers. One of the key advantages of the test method described here is that it enables functional testing of microprocessors on low cost testers. Detailed implementation of this technique, the test generation methodology, the fault grade methodology and silicon results on Intel ®Pentium ®4 and Itanium驴 family microprocessors are presented.