Computer organization & design: the hardware/software interface
Computer organization & design: the hardware/software interface
On the test of microprocessor IP cores
Proceedings of the conference on Design, automation and test in Europe
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A scalable software-based self-test methodology for programmable processors
Proceedings of the 40th annual Design Automation Conference
Instruction Randomization Self Test For Processor Cores
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
FRITS " A Microprocessor Functional BIST Method
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Logic BIST for Large Industrial Designs: Real Issues and Case Studies
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Software-Based Self-Testing of Embedded Processors
IEEE Transactions on Computers
On A Software-Based Self-Test Methodology and Its Application
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Software-Based Self-Test for Pipelined Processors: A Case Study
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Software-based self-testing methodology for processor cores
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A System-layer Infrastructure for SoC Diagnosis
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An novel methodology for reducing SoC test data volume on FPGA-based testers
Proceedings of the conference on Design, automation and test in Europe
Functional self-testing for bus-based symmetric multiprocessors
Proceedings of the conference on Design, automation and test in Europe
Functional processor-based testing of communication peripherals in systems-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Economic analysis of testing homogeneous Manycore chips
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Application-aware diagnosis of runtime hardware faults
Proceedings of the International Conference on Computer-Aided Design
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Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in Systems-on-Chip (SoCs). By moving test related functions from external resources to the SoC's interior, in the form of test programs that the on-chip processor executes, SBST eliminates the need for high-cost testers, and enables high-quality at-speed testing. Thus far, SBST approaches have focused almost exclusively on the functional (directly programmer visible) components of the processor. In this paper, we analyze the challenges involved in testing an important component of modern processors, namely, the pipelining logic, and propose a systematic SBST methodology to address them. We first demonstrate that SBST programs that only target the functional components of the processor are insufficient to test the pipeline logic, resulting in a significant loss of fault coverage. We further identify the testability hotspots in the pipeline logic. Finally, we develop a systematic SBST methodology that enhances existing SBST programs to comprehensively test the pipeline logic. The proposed methodology is complementary to previous SBST techniques that target functional components (their results can form the input to our methodology), and can reuse the test development effort behind existing SBST programs. We applied the methodology to two complex, fully pipelined processors. Results show that our methodology provides fault coverage improvements of up to 15% (12% on average) for the entire processor, and fault coverage improvements of 22% for the pipeline logic, compared to a conventional SBST approach.