A method for generating weighted random test pattern
IBM Journal of Research and Development
On Evaluating and Optimizing Weights for Weighted Random Pattern Testing
IEEE Transactions on Computers
AMULET1: An Asynchronous ARM Microprocessor
IEEE Transactions on Computers
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
ScanBist: A Multifrequency Scan-Based BIST Method
IEEE Design & Test
Functional Testing of Current Microprocessors (applied to the Intel i860TM)
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
An Instruction Sequence Assembling Methodology for Testing Microprocessors
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Functional Testing of Microprocessors
IEEE Transactions on Computers
Test Generation for Microprocessors
IEEE Transactions on Computers
Microprocessor testing by instruction sequences derived from random patterns
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Embedded hardware and software self-testing methodologies for processor cores
Proceedings of the 37th Annual Design Automation Conference
Deterministic software-based self-testing of embedded processor cores
Proceedings of the conference on Design, automation and test in Europe
On the test of microprocessor IP cores
Proceedings of the conference on Design, automation and test in Europe
Instruction-level DFT for testing processor and IP cores in system-on-a-chip
Proceedings of the 38th annual Design Automation Conference
Testing for interconnect crosstalk defects using on-chip embedded processor cores
Proceedings of the 38th annual Design Automation Conference
Embedded software-based self-testing for SoC design
Proceedings of the 39th annual Design Automation Conference
Test of future system-on-chips
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores
Journal of Electronic Testing: Theory and Applications
Embedded Software-Based Self-Test for Programmable Core-Based Designs
IEEE Design & Test
Instruction-Based Self-Testing of Processor Cores
Journal of Electronic Testing: Theory and Applications
A scalable software-based self-test methodology for programmable processors
Proceedings of the 40th annual Design Automation Conference
Test Program Synthesis for Path Delay Faults in Microprocessor Cores
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Improving Fault Coverage in System Tests
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Designing Self Test Programs for Embedded DSP Cores
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores
Journal of Electronic Testing: Theory and Applications
Low-Cost Software-Based Self-Testing of RISC Processor Cores
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Fully Automatic Test Program Generation for Microprocessor Cores
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Software-Based Self-Testing of Embedded Processors
IEEE Transactions on Computers
New evolutionary techniques for test-program generation for complex microprocessor cores
GECCO '05 Proceedings of the 7th annual conference on Genetic and evolutionary computation
A constraint-based solution for on-line testing of processors embedded in real-time applications
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Automatic generation of test sets for SBST of microprocessor IP cores
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Instruction-level test methodology for CPU core self-testing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Software-based self-test methodology for crosstalk faults in processors
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Software-based self-test of processors under power constraints
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A Self Test Program Design Technique for Embedded DSP Cores
Journal of Electronic Testing: Theory and Applications
Software-based self-testing of microprocessors
Journal of Systems Architecture: the EUROMICRO Journal
Systematic software-based self-test for pipelined processors
Proceedings of the 43rd annual Design Automation Conference
Software-based self-testing with multiple-level abstractions for soft processor cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A hybrid software-based self-testing methodology for embedded processor
Proceedings of the 2008 ACM symposium on Applied computing
Testing diagnostics of modern microprocessors with the use of functional models
Automation and Remote Control
Instruction-based self-testing of delay faults in pipelined processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Adaptive online testing for efficient hard fault detection
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Using introspective software-based testing for post-silicon debug and repair
Proceedings of the 47th Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Systematic software-based self-test for pipelined processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Access to embedded processor cores for application of test has greatly complicated the testability of large systems on silicon. Scan based testing methods cannot be applied to processor cores which cannot be modified to meet the design requirements for scan insertion. Instruction Randomization Self Test (IRST) achieves stuck-at-fault coverage for an embedded processor core without the need for scan insertion or mux isolation for application of test patterns. This is a new built-in self test method which combines the execution of microprocessor instructions with a small amount of on-chip test hardware which is used to randomize those instructions. IRST is well suited for meeting the challenges of testing ASIC systems which contain embedded processor cores.