Global routing with crosstalk constraints
DAC '98 Proceedings of the 35th annual Design Automation Conference
Self-test methodology for at-speed test of crosstalk in chip interconnects
Proceedings of the 37th Annual Design Automation Conference
Validation and test generation for oscillatory noise in VLSI interconnects
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Fault modeling and simulation for crosstalk in system-on-chip interconnects
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Interconnect tuning strategies for high-performance ICs
Proceedings of the conference on Design, automation and test in Europe
VHDL: Analysis and Modeling of Digital Systems
VHDL: Analysis and Modeling of Digital Systems
Crosstalk Minimization in Three-Layer HVH Channel Routing
DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test generation in VLSI circuits for crosstalk noise
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An Algorithmic Test Generation Method for Crosstalk Faults in Synchronous Sequential Circuits
ATS '97 Proceedings of the 6th Asian Test Symposium
2.3 Automatic Test Pattern Generation for Crosstalk Glitches in Digital Circuits
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
2.2 Signal Integrity Problems in Deep Submicron Arising from Interconnects between Cores
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Instruction Randomization Self Test For Processor Cores
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
High-level Crosstalk Defect Simulation for System-on-Chip Interconnects
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Test Generation for Crosstalk-Induced Delay in Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Arithmetic built-in self-test for DSP cores
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Software-based self-testing methodology for processor cores
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A scalable software-based self-test methodology for programmable processors
Proceedings of the 40th annual Design Automation Conference
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In deep-submicron technologies, long interconnects play an ever-important role in determining the performance and reliability of core-based system-on-chips (SoCs). Crosstalk effects degrade the integrity of signals traveling on long interconnects and must be addressed during manufacturing testing. External testing for crosstalk is expensive due to the need for high-speed testers. Built-in self-test, while eliminating the need for a high-speed tester, may lead to excessive test overhead as well as overly aggressive testing. To address this problem, we propose a new software-based self-test methodology for system-on-chips (SoC) based on embedded processors. It enables an on-chip embedded processor core to test for crosstalk in system-level interconnects by executing a self-test program in the normal operational mode of the SoC, thereby allowing at-speed testing of interconnect crosstalk defects, while eliminating the need for test overhead and the possibility of over-testing. We have demonstrated the feasibility of this method by applying it to test the interconnects of a processor-memory system. The defect coverage was evaluated using a system-level crosstalk defect simulation method.