Integration, the VLSI Journal
Integration, the VLSI Journal
Modeling and characterization of long on-chip interconnections for high-performance microprocessors
IBM Journal of Research and Development
Self-test methodology for at-speed test of crosstalk in chip interconnects
Proceedings of the 37th Annual Design Automation Conference
Validation and test generation for oscillatory noise in VLSI interconnects
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Fault modeling and simulation for crosstalk in system-on-chip interconnects
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Improving bus test via IDDT and boundary scan
Proceedings of the 38th annual Design Automation Conference
Testing for interconnect crosstalk defects using on-chip embedded processor cores
Proceedings of the 38th annual Design Automation Conference
Modeling and minimization of interconnect energy dissipation in nanometer technologies
Proceedings of the 38th annual Design Automation Conference
Signal integrity fault analysis using reduced-order modeling
Proceedings of the 39th annual Design Automation Conference
Test of future system-on-chips
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores
Journal of Electronic Testing: Theory and Applications
Signal Integrity: Fault Modeling and Testing in High-Speed SoCs
Journal of Electronic Testing: Theory and Applications
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects
Journal of Electronic Testing: Theory and Applications
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing in a Noisy Environment
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Analysis of Interconnect Crosstalk Defect Coverage of Test Sets
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Testing Interconnects for Noise and Skew in Gigahertz SoCs
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Design for Testability in Nanometer Technologies; Searching for Quality
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SOC test architecture optimization for signal integrity faults on core-external interconnects
Proceedings of the 44th annual Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hi-index | 0.00 |
The SIA Roadmap shows a very aggressive drive to deep submicron designs. A significant corner stone in the industries' ability to utilize this tremendous capabilities is the usage of reusable cores. When employing cores, one must be sensitive to the quality of the interconnects which will carry signals between cores and the ASIC portion of the network. In this work we will use an extremely accurate line simulator which solves the transmission line equations derived from Maxwell's equations for the simulation of line systems. We will show that the coupling between bus lines is significant, since the signal delay can be increased and even hazards can occur. Furthermore, these effects depend on the set of input signals of all bus lines and the skew between the individual input signals. The lines' cross sections are taken from the SIA Roadmap going from 0.35 碌m technology design down to 0.10 碌m technology design.