Global routing with crosstalk constraints
DAC '98 Proceedings of the 35th annual Design Automation Conference
Self-test methodology for at-speed test of crosstalk in chip interconnects
Proceedings of the 37th Annual Design Automation Conference
Fault modeling and simulation for crosstalk in system-on-chip interconnects
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Modeling and minimization of interconnect energy dissipation in nanometer technologies
Proceedings of the 38th annual Design Automation Conference
VHDL: Analysis and Modeling of Digital Systems
VHDL: Analysis and Modeling of Digital Systems
Crosstalk Minimization in Three-Layer HVH Channel Routing
DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
2.2 Signal Integrity Problems in Deep Submicron Arising from Interconnects between Cores
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Analysis of Interconnect Crosstalk Defect Coverage of Test Sets
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Methods for Calculating Coupling Noise in Early Design: A Comparative Analysis
ICCD '98 Proceedings of the International Conference on Computer Design
High-level Crosstalk Defect Simulation for System-on-Chip Interconnects
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
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For system-on-chips (SoC) using deep submicron (DSM) technologies, interconnects are becoming critical determinants for performance, reliability and power. Buses and long interconnects being susceptible to crosstalk noise, may lead to functional and timing failures. Existing at-speed interconnect crosstalk test methods propose inserting dedicated interconnect self-test structures in the SoC to generate vectors which have high crosstalk defect coverage. However, these methods may have a prohibitively high area overhead. To reduce this overhead, existing logic BIST structures like LFSRs could be reused to deliver interconnect tests. But, as shown by our experiments, use of LFSR tests achieve poor crosstalk defect coverage. Additionally, it has been shown that the power consumed during testing can potentially become a significant concern.In this paper, we present Logic-Interconnect BIST (LI-BIST), a comprehensive self-test solution for both the logic of the cores and the SoC interconnects. LI-BIST reuses existing logic BIST structures but generates high-quality tests for interconnect crosstalk defects, while minimizing the area overhead and interconnect power consumption. The application of the LI-BIST methodology on example SoCs indicates that LI-BIST is a viable, low-cost, yet comprehensive solution for testing SoCs.