Global routing with crosstalk constraints
DAC '98 Proceedings of the 35th annual Design Automation Conference
Fault modeling and simulation for crosstalk in system-on-chip interconnects
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Crosstalk Minimization in Three-Layer HVH Channel Routing
DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
Test generation in VLSI circuits for crosstalk noise
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An Algorithmic Test Generation Method for Crosstalk Faults in Synchronous Sequential Circuits
ATS '97 Proceedings of the 6th Asian Test Symposium
2.3 Automatic Test Pattern Generation for Crosstalk Glitches in Digital Circuits
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
2.2 Signal Integrity Problems in Deep Submicron Arising from Interconnects between Cores
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Methods for Calculating Coupling Noise in Early Design: A Comparative Analysis
ICCD '98 Proceedings of the International Conference on Computer Design
Testing for interconnect crosstalk defects using on-chip embedded processor cores
Proceedings of the 38th annual Design Automation Conference
Built-in self-test for signal integrity
Proceedings of the 38th annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Embedded software-based self-testing for SoC design
Proceedings of the 39th annual Design Automation Conference
Test of future system-on-chips
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Crosstalk fault detection by dynamic Idd
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores
Journal of Electronic Testing: Theory and Applications
Signal Integrity: Fault Modeling and Testing in High-Speed SoCs
Journal of Electronic Testing: Theory and Applications
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects
Journal of Electronic Testing: Theory and Applications
Analysis of Interconnect Crosstalk Defect Coverage of Test Sets
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Testing Interconnects for Noise and Skew in Gigahertz SoCs
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Extending JTAG for Testing Signal Integrity in SoCs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Using a Periodic Square Wave Test Signal to Detect Crosstalk Faults
IEEE Design & Test
SOC test architecture optimization for signal integrity faults on core-external interconnects
Proceedings of the 44th annual Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Highly compact interconnect test patterns for crosstalk and static faults
IEEE Transactions on Circuits and Systems II: Express Briefs
Highly compact interconnect test patterns for crosstalk and static faults
IEEE Transactions on Circuits and Systems II: Express Briefs
CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems
Journal of Electronic Testing: Theory and Applications
Self-calibrated energy-efficient and reliable channels for on-chip interconnection networks
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
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The effect of crosstalk errors is most significant in high-performance circuits, mandating at-speed testing for crosstalk defects. This paper describes a self-test methodology that we have developed to enable on-chip at-speed testing of crosstalk defects in System-on-Chip interconnects. The self-test methodology is based on the Maximal Aggressor Fault Model [13], that enables testing of the interconnect with a linear number of test patterns. To enable self-testing of the interconnects, we have designed efficient on-chip test generators and error detectors to be embedded in necessary cores; while the test generators generate test vectors for crosstalk faults, the error detectors analyze the transmission of the test sequences received from the interconnects, and detect any transmission errors. We have also designed test controllers to initiate and manage test transactions by activating the appropriate test generators and error detectors, and having error diagnosis capability. We have developed, simulated, and synthesized parameterized HDL models of the self-test structures. We have applied the self-test methodology to test crosstalk defects in the buses of a DSP chip. Using a new high-level crosstalk simulation technique, we have validated the self-test methodology, including the self-test structures inserted in the DSP chip.