IEEE Spectrum
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
PRIMA: passive reduced-order interconnect macromodeling algorithm
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Full-chip verification of UDSM designs
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Interleaving buffer insertion and transistor sizing into a single optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Projective convolution: RLC model-order reduction using the impulse response
DATE '99 Proceedings of the conference on Design, automation and test in Europe
ENOR: model order reduction of RLC circuits using nodal equations for efficient factorization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Dealing with inductance in high-speed chip design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Universal delay test sets for logic networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-chip inductance modeling and analysis
Proceedings of the 37th Annual Design Automation Conference
Self-test methodology for at-speed test of crosstalk in chip interconnects
Proceedings of the 37th Annual Design Automation Conference
Fault modeling and simulation for crosstalk in system-on-chip interconnects
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Built-in self-test for signal integrity
Proceedings of the 38th annual Design Automation Conference
Digital Design: Principles and Practices
Digital Design: Principles and Practices
Analysis and Design of Analog Integrated Circuits
Analysis and Design of Analog Integrated Circuits
Process Variations and their Impact on Circuit Operation
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Test generation in VLSI circuits for crosstalk noise
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Tutorial: Delay Fault Models and Coverage
VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing
Interconnect Optimization Strategies for High-Performance VLSI Designs
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Estimation of Switching Noise on Power Supply Lines in Deep Sub-micron CMOS Circuits
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Crosstalk Noise Verification in Digital Designs with Interconnect Process Variations
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
2.2 Signal Integrity Problems in Deep Submicron Arising from Interconnects between Cores
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A Digital BIST for Operational Amplifiers Embedded in Mixed-Signal Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Minimal buffer insertion in clock trees with skew and slew rate constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient linear circuit analysis by Pade approximation via the Lanczos process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Journal of Electronic Testing: Theory and Applications
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As we approach 100 nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-on-chips. Voltage distortion (noise) and delay violations (skew) contribute to the signal integrity loss and ultimately functional error, performance degradation and reliability problems. In this paper, we first define a model for integrity faults on the high-speed interconnects. Then, we present a BIST-based test methodology that includes two special cells to detect and measure noise and skew occurring on the interconnects of the gigahertz system-on-chips. Using an inexpensive test architecture the integrity information accumulated by these special cells can be scanned out for final test and reliability analysis.