AWESpice: a general tool for the accurate and efficient simulation of interconnect problems
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Reduced-order modeling of large linear subcircuits via a block Lanczos algorithm
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Generating sparse partial inductance matrices with guaranteed stability
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Stable and efficient reduction of substrate model networks using congruence transforms
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Zeros and passivity of Arnoldi-reduced-order models for interconnect networks
DAC '97 Proceedings of the 34th annual Design Automation Conference
Preservation of passivity during RLC network reduction via split congruence transformations
DAC '97 Proceedings of the 34th annual Design Automation Conference
Efficient linear circuit analysis by Pade approximation via the Lanczos process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Zeros and passivity of Arnoldi-reduced-order models for interconnect networks
DAC '97 Proceedings of the 34th annual Design Automation Conference
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Timing metrics for physical design of deep submicron technologies
ISPD '98 Proceedings of the 1998 international symposium on Physical design
DAC '98 Proceedings of the 35th annual Design Automation Conference
Tools and methodology for RF IC design
DAC '98 Proceedings of the 35th annual Design Automation Conference
PRIMO: probability interpretation of moments for delay calculation
DAC '98 Proceedings of the 35th annual Design Automation Conference
TETA: transistor-level engine for timing analysis
DAC '98 Proceedings of the 35th annual Design Automation Conference
h-gamma: an RC delay metric based on a gamma distribution approximation of the homogeneous response
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Multipoint moment matching model for multiport distributed interconnect networks
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Reduced-order modelling of linear time-varying systems
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Determination of worst-case aggressor alignment for delay calculation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Coupled noise estimation for distributed RC interconnect model
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Projective convolution: RLC model-order reduction using the impulse response
DATE '99 Proceedings of the conference on Design, automation and test in Europe
An efficient Lyapunov equation-based approach for generating reduced-order models of interconnect
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Error bounded Padé approximation via bilinear conformal transformation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Model-reduction of nonlinear circuits using Krylov-space techniques
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
ENOR: model order reduction of RLC circuits using nodal equations for efficient factorization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Interconnect analysis: from 3-D structures to circuit models
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
IC analyses including extracted inductance models
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
On-chip inductance modeling and analysis
Proceedings of the 37th Annual Design Automation Conference
A rank-one update method for efficient processing of interconnect parasitics in timing analysis
Proceedings of the 37th Annual Design Automation Conference
On switch factor based analysis of coupled RC interconnects
Proceedings of the 37th Annual Design Automation Conference
Projection frameworks for model reduction of weakly nonlinear systems
Proceedings of the 37th Annual Design Automation Conference
A realizable driving point model for on-chip interconnect with inductance
Proceedings of the 37th Annual Design Automation Conference
ClariNet: a noise analysis tool for deep submicron design
Proceedings of the 37th Annual Design Automation Conference
Critical path analysis using a dynamically bounded delay model
Proceedings of the 37th Annual Design Automation Conference
Proceedings of the 37th Annual Design Automation Conference
TICER: realizable reduction of extracted RC circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
The Chebyshev expansion based passive model for distributed interconnect networks
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Model reduction for DC solution of large nonlinear circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Efficient model reduction of interconnect via approximate system gramians
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Modeling crosstalk noise for deep submicron verification tools
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Hierarchical model order reduction for signal-integrity interconnect synthesis
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
An efficient model for frequency-dependent on-chip inductance
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
An optimum fitting algorithm for generation of reduced-order models
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Inductance 101: analysis and design issues
Proceedings of the 38th annual Design Automation Conference
Driver modeling and alignment for worst-case delay noise
Proceedings of the 38th annual Design Automation Conference
Estimation of power distribution in VLSI interconnects
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Geometrically parameterized interconnect performance models for interconnect synthesis
Proceedings of the 2002 international symposium on Physical design
Guaranteed passive balancing transformations for model order reduction
Proceedings of the 39th annual Design Automation Conference
Signal integrity fault analysis using reduced-order modeling
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Efficient switching window computation for cross-talk noise
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Reduced Order Modeling for RLC Interconnect Tree Using Hurwitz Polynomial
Analog Integrated Circuits and Signal Processing
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Signal Integrity: Fault Modeling and Testing in High-Speed SoCs
Journal of Electronic Testing: Theory and Applications
Minimum delay optimization for domino logic circuits---a coupling-aware approach
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A fast simulation approach for inductive effects of VLSI interconnects
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Krylov subspace techniques for reduced-order modeling of large-scale dynamical systems
Applied Numerical Mathematics
A precorrected-FFT method for simulating on-chip inductance
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Noise propagation and failure criteria for VLSI designs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Piecewise polynomial nonlinear model reduction
Proceedings of the 40th annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cross-Coupled Noise Propagation in VLSI Designs
Analog Integrated Circuits and Signal Processing
Driver modeling and alignment for worst-case delay noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Coupling delay optimization by temporal decorrelation using dual threshold voltage technique
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Automated, Accurate Macromodelling of Digital Aggressors for Power/Ground/Substrate Noise Prediction
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Variational delay metrics for interconnect timing analysis
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 41st annual Design Automation Conference
Equivalent Waveform Propagation for Static Timing Analysis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Branch Merge Reduction of RLCM Networks
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A complete methodology for an accurate static noise analysis
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Operator-based model-order reduction of linear periodically time-varying systems
Proceedings of the 42nd annual Design Automation Conference
A quasi-convex optimization approach to parameterized model order reduction
Proceedings of the 42nd annual Design Automation Conference
Supply Voltage Degradation Aware Analytical Placement
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
SPRIM: structure-preserving reduced-order interconnect macromodeling
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A robust cell-level crosstalk delay change analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
An unconditional stable general operator splitting method for transistor level transient analysis
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Macromodelling oscillators using Krylov-subspace methods
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Efficient transient simulation for transistor-level analysis
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Efficient decoupling capacitor planning via convex programming methods
Proceedings of the 2006 international symposium on Physical design
SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Time domain model order reduction by wavelet collocation method
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Non-gaussian statistical interconnect timing analysis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
Integration, the VLSI Journal
Efficient computation of current flow in signal wires for reliability analysis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Generic sub-space algorithm for generating reduced order models of linear time varying vlsi circuits
Proceedings of the 18th ACM Great Lakes symposium on VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Transistor level gate modeling for accurate and fast timing, noise, and power analysis
Proceedings of the 45th annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Statistical static timing analysis: A survey
Integration, the VLSI Journal
Fast interconnect and gate timing analysis for performance optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Stochastic power/ground supply voltage prediction and optimization via analytical placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Stable parallelizable model order reduction for circuits with frequency-dependent elements
IEEE Transactions on Circuits and Systems Part I: Regular Papers
QLMOR: a new projection-based approach for nonlinear model order reduction
Proceedings of the 2009 International Conference on Computer-Aided Design
Numerical Simulation and Modelling of Electronic and Biochemical Systems
Foundations and Trends in Electronic Design Automation
Passive reduced order modeling of multiport interconnects via semidefinite programming
Proceedings of the Conference on Design, Automation and Test in Europe
Manifold construction and parameterization for nonlinear manifold-based model reduction
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
State-space analytical modelling for on-chip coupling effects
ICC'06 Proceedings of the 10th WSEAS international conference on Circuits
Model order reduction via eigen decomposition analysis
International Journal of Computer Applications in Technology
Structure preserving reduced-order modeling of linear periodic time-varying systems
Proceedings of the International Conference on Computer-Aided Design
Generalized nonlinear timing/phase macromodeling: theory, numerical methods and applications
Proceedings of the International Conference on Computer-Aided Design
Power supply selective mapping for accurate timing analysis
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Journal of Electronic Testing: Theory and Applications
High-performance gate sizing with a signoff timer
Proceedings of the International Conference on Computer-Aided Design
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This paper describes PRIMA, an algorithm for generating provably passive reduced order N-port models for RLC interconnect circuits. It is demonstrated that, in addition to requiring macromodel stability, macromodel passivity is needed to guarantee the overall circuit stability once the active and passive driver/load models are connected. PRIMA extends the block Arnoldi technique to include guaranteed passivity. Moreover, it is empirically observed that the accuracy is superior to existing block Arnoldi methods. While the same passivity extension is not possible for MPVL, we observed comparable accuracy in the frequency domain for all examples considered. Additionally a path tracing algorithm is used to calculate the reduced order macromodel with the utmost efficiency for generalized RLC interconnects.