GMRES: a generalized minimal residual algorithm for solving nonsymmetric linear systems
SIAM Journal on Scientific and Statistical Computing
Efficient linear circuit analysis by Pade´ approximation via the Lanczos process
EURO-DAC '94 Proceedings of the conference on European design automation
Efficient reduced-order modeling for the transient simulation of three-dimensional interconnect
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Package and interconnect modeling of the HFA3624, a 2.4GHz RF to IF converter
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Preservation of passivity during RLC network reduction via split congruence transformations
DAC '97 Proceedings of the 34th annual Design Automation Conference
PRIMA: passive reduced-order interconnect macromodeling algorithm
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Timing metrics for physical design of deep submicron technologies
ISPD '98 Proceedings of the 1998 international symposium on Physical design
DAC '98 Proceedings of the 35th annual Design Automation Conference
PRIMO: probability interpretation of moments for delay calculation
DAC '98 Proceedings of the 35th annual Design Automation Conference
h-gamma: an RC delay metric based on a gamma distribution approximation of the homogeneous response
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Determination of worst-case aggressor alignment for delay calculation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Projective convolution: RLC model-order reduction using the impulse response
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Model order-reduction of RC(L) interconnect including variational analysis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Interconnect analysis: from 3-D structures to circuit models
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
IC analyses including extracted inductance models
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A rank-one update method for efficient processing of interconnect parasitics in timing analysis
Proceedings of the 37th Annual Design Automation Conference
On switch factor based analysis of coupled RC interconnects
Proceedings of the 37th Annual Design Automation Conference
Projection frameworks for model reduction of weakly nonlinear systems
Proceedings of the 37th Annual Design Automation Conference
A realizable driving point model for on-chip interconnect with inductance
Proceedings of the 37th Annual Design Automation Conference
Critical path analysis using a dynamically bounded delay model
Proceedings of the 37th Annual Design Automation Conference
A scalable substrate noise coupling model for mixed-signal ICs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Practical considerations for passive reduction of RLC circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Interconnect parasitic extraction in the digital IC design methodology
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Estimation of power distribution in VLSI interconnects
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Geometrically parameterized interconnect performance models for interconnect synthesis
Proceedings of the 2002 international symposium on Physical design
A factorization-based framework for passivity-preserving model reduction of RLC systems
Proceedings of the 39th annual Design Automation Conference
Minimum delay optimization for domino logic circuits---a coupling-aware approach
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient model order reduction via multi-node moment matching
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
NORM: compact model order reduction of weakly nonlinear systems
Proceedings of the 40th annual Design Automation Conference
Piecewise polynomial nonlinear model reduction
Proceedings of the 40th annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Coupling delay optimization by temporal decorrelation using dual threshold voltage technique
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Improved model-order reduction by using spacial information in moments
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Direct Nonlinear Order Reduction with Variational Analysis
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Analog Macromodeling using Kernel Methods
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A Hybrid Approach to Nonlinear Macromodel Generation for Time-Varying Analog Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A General S-Domain Hierarchical Network Reduction Algorithm
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Analytic Modeling of Interconnects for Deep Sub-Micron Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Parameter independent model order reduction
Mathematics and Computers in Simulation
Stochastic analysis of interconnect performance in the presence of process variations
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Model order reduction of linear networks with massive ports via frequency-dependent port packing
Proceedings of the 43rd annual Design Automation Conference
Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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