RICE: Rapid interconnect circuit evaluator
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A gate-delay model for high-speed CMOS circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
The Elmore delay as bound for RC trees with generalized input signals
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Stable and efficient reduction of substrate model networks using congruence transforms
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Coping with RC(L) interconnect design headaches
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
An explicit RC-circuit delay approximation based on the first three moments of the impulse response
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Analytical delay models for VLSI interconnects under ramp input
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Calculating worst-case gate delays due to dominant capacitance coupling
DAC '97 Proceedings of the 34th annual Design Automation Conference
PRIMA: passive reduced-order interconnect macromodeling algorithm
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
PRIMO: probability interpretation of moments for delay calculation
DAC '98 Proceedings of the 35th annual Design Automation Conference
Timing Verification and Optimization for the PowerPCTM Processor Family
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Efficient linear circuit analysis by Pade approximation via the Lanczos process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
h-gamma: an RC delay metric based on a gamma distribution approximation of the homogeneous response
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A two moment RC delay metric for performance optimization
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Transformational placement and synthesis
DATE '00 Proceedings of the conference on Design, automation and test in Europe
An "effective" capacitance based delay metric for RC interconnect
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A delay metric for RC circuits based on the Weibull distribution
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Delay and slew metrics using the lognormal distribution
Proceedings of the 40th annual Design Automation Conference
Fitted Elmore delay: a simple and accurate interconnect delay model
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interconnect delay and slew metrics using the beta distribution
Proceedings of the Conference on Design, Automation and Test in Europe
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Performance-driven physical design is becoming more important as advances in IC technologies enable gigahertz operating frequencies. These same IC technologies, however, exhibit dominant interconnect resistance, non-negligible coupling capacitance, and even the potential for inductance effects, which makes the performance modeling and prediction more difficult. In this tutorial paper we will overview some of the existing timing metrics that are suitable for use during physical design, and introduce new metrics and directions for future work.