Fitted Elmore delay: a simple and accurate interconnect delay model

Authors:
Arif Ishaq Abou-Seido;Brian Nowak;Chris Chu
Affiliations:
Intel Corporation, Santa Clara, CA;IBM Corporation, Rochester, MN;Department of Electrical and Computer Engineering, Iowa State University, Ames, IA
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2004

Citing 16
Cited 16

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Abstract

In this brief, we present a new interconnect delay model called fitted Elmore delay (FED). FED is generated by approximating HSPICE delay data using a curve fitting technique. The functional form used in curve fitting is derived based on the Elmore delay (ED) model. Thus, our model has all the advantages of the ED model. It has a closed-form expression as simple as the ED model and is extremely efficient to compute. Interconnect optimization with respect to design parameters can also be done as easily as in the ED model. In fact, most previous algorithms and programs based on ED model can use our model without much change. Most importantly, FED is significantly more accurate than the ED model. The maximum error in delay estimation is at most 2% for our model, compared to 8.5% for the scaled ED model. The average error is less than 0.8%. We also show that FED can be more than 10 times more accurate than the ED model when applied to wire sizing.