An explicit RC-circuit delay approximation based on the first three moments of the impulse response
DAC '96 Proceedings of the 33rd annual Design Automation Conference
PRIMO: probability interpretation of moments for delay calculation
DAC '98 Proceedings of the 35th annual Design Automation Conference
h-gamma: an RC delay metric based on a gamma distribution approximation of the homogeneous response
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Delay Models for MCM Interconnects when Response is Non-Monotone
MCMC '97 Proceedings of the 1997 Conference on IEEE Multi-Chip Module Conference
Fitted Elmore delay: a simple and accurate interconnect delay model
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Elmore model for energy estimation in RC trees
Proceedings of the 43rd annual Design Automation Conference
Integration, the VLSI Journal
Self-heating-aware optimal wire sizing under Elmore delay model
Proceedings of the conference on Design, automation and test in Europe
Zero skew clock routing in X-architecture based on an improved greedy matching algorithm
Integration, the VLSI Journal
Timing-driven via placement heuristics for three-dimensional ICs
Integration, the VLSI Journal
Modelling of parasitic interconnection inductances on the GaAs-based VLSIC's
Mathematical and Computer Modelling: An International Journal
The Elmore delay as a bound for RC trees with generalized input signals
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An analytical delay model for RLC interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Asymptotic waveform evaluation for timing analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Equivalent Elmore delay for RLC trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RC delay metrics for performance optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An interconnect energy model considering coupling effects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Maze routing with buffer insertion and wiresizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Signal Delay in RC Tree Networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Wire Sizing for Non-Tree Topology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Wire Retiming Problem With Net Topology Optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Elmore delay metric is a widely used model to compute signal delays for both analog and digital circuit interconnects. Although it provides a limited accuracy and its applicability is limited to the step function type input signals, this model is extremely popular with simple analytical functions that can be easily incorporated into design and automation software. In this work, a new boundary limiting the Elmore delay is introduced. A general form of traditional Elmore delay is defined and solved by utilizing this boundary. The new solution of the propagation delay problem called the improved Elmore delay model is derived according to the compound interest problem of Jacob Bernoulli. The improved Elmore delay formulation and the traditional Elmore delay model are compared according to SPICE simulation environment performances which verifies the superior accuracy of the novel delay formulation. The test results proved that better accuracy is achieved with the improved Elmore delay model than the traditional Elmore delay model with the same computation speed.