Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Delay and Power Expressions for a CMOS Inverter Drivinga Resistive-Capacitive Load
Analog Integrated Circuits and Signal Processing - Special issue: analog design issues in digital VSLI circuits and systems
Simple metrics for slew rate of RC circuits based on two circuit moments
Proceedings of the 40th annual Design Automation Conference
Library Compatible Ceff for Gate-Level Timing
Proceedings of the conference on Design, automation and test in Europe
The Elmore delay as a bound for RC trees with generalized input signals
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Delay and current estimation in a CMOS inverter with an RC load
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Transition time modeling in deep submicron CMOS
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An improved Elmore delay model for VLSI interconnects
Mathematical and Computer Modelling: An International Journal
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The delay of on-chip interconnect wiring is having an important influence on the timing performance of logic path. This is particularly true where drivers are connected through a non-negligible length of wire. If the Elmore resistance-capacitance delay model remains popular due to its simple formulation, limitations have been shown in sub-micrometer domain due to its inability in capturing input slope and shielding effects.This paper presents an analytical expression for the transition time and the switching delay of an RC interconnect, including the line input and output drivers. Based on a previously developed model of the inverter transition time and the switching delay, we propose a model of the shielding capacitance effect on the input driver. We then determine the transition time of the output driver and the switching delay of the complete structure for different size of input drivers. We validate these analytical expressions with respect to electrical simulations, on 130 and 90 nm processes, using the eldo's transmission line model.