The Elmore delay as bound for RC trees with generalized input signals
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Efficient coupled noise estimation for on-chip interconnects
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Table-lookup methods for improved performance-driven routing
DAC '98 Proceedings of the 35th annual Design Automation Conference
h-gamma: an RC delay metric based on a gamma distribution approximation of the homogeneous response
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Shaping a VLSI wire to minimize delay using transmission line model
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A two moment RC delay metric for performance optimization
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Realizable reduction for RC interconnect circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
An analytic calculation method for delay time of RC-class interconnects
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
RC(L) interconnect sizing with second order considerations via posynomial programming
Proceedings of the 2001 international symposium on Physical design
Min/max on-chip inductance models and delay metrics
Proceedings of the 38th annual Design Automation Conference
PERI: a technique for extending delay and slew metrics to ramp inputs
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
An "effective" capacitance based delay metric for RC interconnect
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Closed form expressions for extending step delay and slew metrics to ramp inputs
Proceedings of the 2003 international symposium on Physical design
An Approach to Energy Consumption Modeling in RC Ladder Circuits
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
A delay metric for RC circuits based on the Weibull distribution
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Delay and slew metrics using the lognormal distribution
Proceedings of the 40th annual Design Automation Conference
Simple metrics for slew rate of RC circuits based on two circuit moments
Proceedings of the 40th annual Design Automation Conference
Closed-Form Crosstalk Noise Delay Metrics
Analog Integrated Circuits and Signal Processing
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Evaluation of energy consumption in RC ladder circuits driven by a ramp input
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Robust analytical gate delay modeling for low voltage circuits
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Integration, the VLSI Journal
Digital Circuit Optimization via Geometric Programming
Operations Research
An accurate slew metric for on-chip VLSI interconnect using Weibull distribution function
Proceedings of the International Conference on Advances in Computing, Communication and Control
Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect delay and slew metrics using the beta distribution
Proceedings of the Conference on Design, Automation and Test in Europe
Energy consumption in RC tree circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
State-space analytical modelling for on-chip coupling effects
ICC'06 Proceedings of the 10th WSEAS international conference on Circuits
Energy consumption in RC tree circuits with exponential inputs: an analytical model
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
An improved Elmore delay model for VLSI interconnects
Mathematical and Computer Modelling: An International Journal
Predictability for timing and temperature in multiprocessor system-on-chip platforms
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
TAU 2013 variation aware timing analysis contest
Proceedings of the 2013 ACM international symposium on International symposium on physical design
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The Elmore delay is an extremely popular timing-performance metric which is used at all levels of electronic circuit design automation, particularly for resistor-capacitor (RC) tree analysis. The widespread usage of this metric is mainly attributable to it being a delay measure that is a simple analytical function of the circuit parameters. The only drawback to this delay metric is the uncertainty of its accuracy and the restriction to it being an estimate only for the step response delay. In this paper, we prove that the Elmore delay measure is an absolute upper bound on the actual 50% delay of an RC tree response. Moreover, we prove that this bound holds for input signals other than steps and that the actual delay asymptotically approaches the Elmore delay as the input signal rise time increases. A lower bound on the delay is also developed using the Elmore delay and the second moment of the impulse response. The utility of this bound is for understanding the accuracy and the limitations of the Elmore metric as we use it as a performance metric for design automation