Generalized moment-matching methods for transient analysis of interconnect networks
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Optimal equivalent circuits for interconnect delay calculations using moments
EURO-DAC '94 Proceedings of the conference on European design automation
Reduced-order modeling of large linear subcircuits via a block Lanczos algorithm
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Stable and efficient reduction of substrate model networks using congruence transforms
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Reduced-order modeling of large passive linear circuits by means of the SYPVL algorithm
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Lumped interconnect models via Gaussian quadrature
DAC '97 Proceedings of the 34th annual Design Automation Conference
Signal delay in RC tree networks
DAC '81 Proceedings of the 18th Design Automation Conference
The Elmore delay as a bound for RC trees with generalized input signals
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Aggressive crunching of extracted RC netlists
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Reduced Order Modeling for RLC Interconnect Tree Using Hurwitz Polynomial
Analog Integrated Circuits and Signal Processing
Hurwitz stable reduced order modeling for RLC interconnect trees
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Explicit gate delay model for timing evaluation
Proceedings of the 2003 international symposium on Physical design
Realizable RLCK circuit crunching
Proceedings of the 40th annual Design Automation Conference
Shielding effect of on-chip interconnect inductance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Interconnect reduction is an important step in the design and analysis of complex interconnects found in present-day integrated circuits. This paper presents techniques for obtaining realizable and accurate reduced models for two-port and multi-port RC circuits. The proposed method is also particularly suitable for interconnect reduction for nonlinear circuit simulation and for interconnect post-processing in a parasitic extractor. The method has two limitations. First, it only considers the first few moments of the transfer function; however, that is accurate enough for RC circuits. Second, the amount of interconnect reduction is topology dependent. Although, most on-chip interconnect topologies are well suited for the method proposed. Accuracy and efficiency of the proposed method is demonstrated for various realistic examples.