AWESpice: a general tool for the accurate and efficient simulation of interconnect problems
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Reduced-order modeling of large linear subcircuits via a block Lanczos algorithm
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Stable and efficient reduction of substrate model networks using congruence transforms
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Reduced-order modeling of large passive linear circuits by means of the SYPVL algorithm
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
TICER: realizable reduction of extracted RC circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Realizable reduction for RC interconnect circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Signal delay in RC tree networks
DAC '81 Proceedings of the 18th Design Automation Conference
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient methods for large resistor networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a short-and-update technique for resistors (possibly connected to sinks) that can further crunch the RC network effectively after eliminating internal nodes [1,14]. Our method produces a realizable RC circuit and preserves the total capacitance in the network. While our technique cannot guarantee preserving the Elmore delay at each network sink node, the maximum delay error can be controlled by the user. Our method provides a smooth tradeoff between run time and delay accuracy, ranging from full retention of all resistors to complete elimination.