Fundamentals of computer-aided circuit simulation
Fundamentals of computer-aided circuit simulation
Introduction to algorithms
An Approximate Minimum Degree Ordering Algorithm
SIAM Journal on Matrix Analysis and Applications
Matrix computations (3rd ed.)
TICER: realizable reduction of extracted RC circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Computer-Aided Analysis of Electronic Circuits: Algorithms and Computational Techniques
Computer-Aided Analysis of Electronic Circuits: Algorithms and Computational Techniques
Aggressive crunching of extracted RC netlists
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Realizable parasitic reduction using generalized Y-Δ transformation
Proceedings of the 40th annual Design Automation Conference
Realizable RLCK circuit crunching
Proceedings of the 40th annual Design Automation Conference
Algorithm 836: COLAMD, a column approximate minimum degree ordering algorithm
ACM Transactions on Mathematical Software (TOMS)
Algorithm 837: AMD, an approximate minimum degree ordering algorithm
ACM Transactions on Mathematical Software (TOMS)
SPRIM: structure-preserving reduced-order interconnect macromodeling
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Minimizing Effective Resistance of a Graph
SIAM Review
Poor man's TBR: a simple model reduction scheme
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Realizable reduction of interconnect circuits including self and mutual inductances
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Realizable Reduction of RC Networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Large resistor networks arise during the design of very-large-scale integration chips as a result of parasitic extraction and electro static discharge analysis. Simulating these large parasitic resistor networks is of vital importance, since it gives an insight into the functional and physical performance of the chip. However, due to the increasing amount of interconnect and metal layers, these networks may contain millions of resistors and nodes, making accurate simulation time consuming or even infeasible. We propose efficient algorithms for three types of analysis of large resistor networks: 1) computation of path resistances; 2) computation of resistor currents; and 3) reduction of resistor networks. The algorithms are exact, orders of magnitude faster than conventional approaches, and enable simulation of very large networks.