Realizable Reduction of RC Networks

Authors:
B. N. Sheehan
Affiliations:
Mentor Graphics Corp., Wilsonville
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2007

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Abstract

In this paper, we develop from various points of view the time-constant equilibration reduction (TICER) algorithm, a circuit-reduction method that converts a given network into a smaller network (one with fewer nodes and branches) by eliminating nodes that have few neighbors and small nodal time constants. Advantages of TICER include: great efficiency, intuitive error control, preservation of sparsity, output in the form of an network, and the ability to handle networks with many ports.