Power grid reduction based on algebraic multigrid principles
Proceedings of the 40th annual Design Automation Conference
Realizable parasitic reduction using generalized Y-Δ transformation
Proceedings of the 40th annual Design Automation Conference
Realizable RLCK circuit crunching
Proceedings of the 40th annual Design Automation Conference
Fast flip-chip power grid analysis via locality and grid shells
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Locally adapted hierarchical basis preconditioning
ACM SIGGRAPH 2006 Papers
Multigrid on GPU: tackling power grid analysis on parallel SIMT platforms
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 47th Design Automation Conference
Multigrid and multilevel preconditioners for computational photography
Proceedings of the 2011 SIGGRAPH Asia Conference
A multigrid-like technique for power grid analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Realizable Reduction of RC Networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Parallel On-Chip Power Distribution Network Analysis on Multi-Core-Multi-GPU Platforms
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scalable vectorless power grid current integrity verification
Proceedings of the 50th Annual Design Automation Conference
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Realizable power grid reduction becomes key to efficient design and verification of nowadays large-scale power delivery networks (PDNs). Existing state-of-the-art realizable reduction techniques for interconnect circuits, such as TICER algorithm, can not be well suited for effective power grid reductions, since reducing the mesh-structured power grids by TICER's nodal elimination scheme may introduce excessive number of new edges in the reduced grids that can be even harder to solve than the original grid due to the drastically increased sparse matrix density. In this work, we present a novel geometric template based reduction technique for reducing large-scale flip-chip power grids. Our method first creates geometric template according to the original power grid topology and then performs novel iterative grid corrections to improve the accuracy by matching the electrical behaviors of the reduced template grid with the original grid. Our experimental results show that the proposed reduction method can reduce industrial power grid designs by up to 95% with very satisfactory solution quality.